llvm-project.git/llvm/test/CodeGen/AMDGPU/optimize-compare.mir, branch users/nico/python-2

[MIRPrinter] Don't print line break when there is no instructions (NFC) (#80147)

2024-02-01T14:10:52+00:00

Per #80143, we can remove the extra line break when there is no
instruction.

[AMDGPU,test] Change llc -march= to -mtriple= (#75982)

2024-01-17T05:54:58+00:00

Similar to 806761a7629df268c8aed49657aeccffa6bca449.

For IR files without a target triple, -mtriple= specifies the full
target triple while -march= merely sets the architecture part of the
default target triple, leaving a target triple which may not make sense,
e.g. amdgpu-apple-darwin.

Therefore, -march= is error-prone and not recommended for tests without
a target triple. The issue has been benign as we recognize
$unknown-apple-darwin as ELF instead of rejecting it outrightly.

This patch changes AMDGPU tests to not rely on the default
OS/environment components. Tests that need fixes are not changed:

```
  LLVM :: CodeGen/AMDGPU/fabs.f64.ll
  LLVM :: CodeGen/AMDGPU/fabs.ll
  LLVM :: CodeGen/AMDGPU/floor.ll
  LLVM :: CodeGen/AMDGPU/fneg-fabs.f64.ll
  LLVM :: CodeGen/AMDGPU/fneg-fabs.ll
  LLVM :: CodeGen/AMDGPU/r600-infinite-loop-bug-while-reorganizing-vector.ll
  LLVM :: CodeGen/AMDGPU/schedule-if-2.ll
```

llvm-reduce: Don't assert on functions which don't track liveness

2022-06-07T14:00:25+00:00

Use the query that doesn't assert if TracksLiveness isn't set, which
needs to always be available. We also need to start printing liveins
regardless of TracksLiveness.

AMDGPU: Remove some invalid kill flags in tests

2022-05-03T23:05:15+00:00

These killed registers need to be live out of the block but the
verifier wasn't catching it.

AMDGPU: Regenerate test checks

2022-05-03T23:05:15+00:00

[AMDGPU] Process any power of 2 in optimizeCompareInstr

2021-09-03T00:39:17+00:00

Differential Revision: https://reviews.llvm.org/D109201

[AMDGPU] Fold immediates in the optimizeCompareInstr

2021-09-03T00:23:26+00:00

Peephole works before the first SIFoldOperands so most of
the immediates are in registers.

Differential Revision: https://reviews.llvm.org/D109186

[AMDGPU] Use S_BITCMP0_* to replace AND in optimizeCompareInstr

2021-09-02T16:38:01+00:00

These can be used for reversed conditions if result of the AND
is unused except in the compare:

s_cmp_eq_u32 (s_and_b32 $src, 1), 0 => s_bitcmp0_b32 $src, 0
s_cmp_eq_i32 (s_and_b32 $src, 1), 0 => s_bitcmp0_b32 $src, 0
s_cmp_eq_u64 (s_and_b64 $src, 1), 0 => s_bitcmp0_b64 $src, 0
s_cmp_lg_u32 (s_and_b32 $src, 1), 1 => s_bitcmp0_b32 $src, 0
s_cmp_lg_i32 (s_and_b32 $src, 1), 1 => s_bitcmp0_b32 $src, 0
s_cmp_lg_u64 (s_and_b64 $src, 1), 1 => s_bitcmp0_b64 $src, 0

Differential Revision: https://reviews.llvm.org/D109099

[AMDGPU] Use S_BITCMP1_* to replace AND in optimizeCompareInstr

2021-09-01T22:59:12+00:00

Differential Revision: https://reviews.llvm.org/D109082

[AMDGPU] Introduce optimizeCompareInstr

2021-09-01T22:57:05+00:00

The following patterns are currently handled:

s_cmp_eq_u32 (s_and_b32 $src, 1), 1 => s_and_b32 $src, 1
s_cmp_eq_i32 (s_and_b32 $src, 1), 1 => s_and_b32 $src, 1
s_cmp_eq_u64 (s_and_b64 $src, 1), 1 => s_and_b64 $src, 1
s_cmp_ge_u32 (s_and_b32 $src, 1), 1 => s_and_b32 $src, 1
s_cmp_ge_i32 (s_and_b32 $src, 1), 1 => s_and_b32 $src, 1
s_cmp_lg_u32 (s_and_b32 $src, 1), 0 => s_and_b32 $src, 1
s_cmp_lg_i32 (s_and_b32 $src, 1), 0 => s_and_b32 $src, 1
s_cmp_lg_u64 (s_and_b64 $src, 1), 0 => s_and_b64 $src, 1
s_cmp_gt_u32 (s_and_b32 $src, 1), 0 => s_and_b32 $src, 1
s_cmp_gt_i32 (s_and_b32 $src, 1), 0 => s_and_b32 $src, 1

Differential Revision: https://reviews.llvm.org/D109031