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<title>llvm-project.git/llvm/test/CodeGen/AMDGPU/loop-prefetch-data.ll, branch main</title>
<subtitle>Unnamed repository; edit this file 'description' to name the repository.
</subtitle>
<link rel='alternate' type='text/html' href='https://git.belthelziquor.com/llvm-project.git/'/>
<entry>
<title>[AMDGPU] Enable multi-group xnack replay in hardware (GFX1250) (#169016)</title>
<updated>2025-11-21T14:12:17+00:00</updated>
<author>
<name>Christudasan Devadasan</name>
<email>christudasan.devadasan@amd.com</email>
</author>
<published>2025-11-21T14:12:17+00:00</published>
<link rel='alternate' type='text/html' href='https://git.belthelziquor.com/llvm-project.git/commit/?id=a2dc4e02e7ba77ddcb0afca0304535d8f142c98b'/>
<id>a2dc4e02e7ba77ddcb0afca0304535d8f142c98b</id>
<content type='text'>
This patch enables the multi-group xnack replay mode by
configuring the hardware MODE register at kernel entry.
This aligns the hardware behavior with the compiler's
existing multi-group s_wait_xcnt insertion logic.</content>
<content type='xhtml'>
<div xmlns='http://www.w3.org/1999/xhtml'>
<pre>
This patch enables the multi-group xnack replay mode by
configuring the hardware MODE register at kernel entry.
This aligns the hardware behavior with the compiler's
existing multi-group s_wait_xcnt insertion logic.</pre>
</div>
</content>
</entry>
<entry>
<title>[AMDGPU][SDAG] Only fold flat offsets if they are inbounds PTRADDs (#165427)</title>
<updated>2025-11-19T10:48:12+00:00</updated>
<author>
<name>Fabian Ritter</name>
<email>fabian.ritter@amd.com</email>
</author>
<published>2025-11-19T10:48:12+00:00</published>
<link rel='alternate' type='text/html' href='https://git.belthelziquor.com/llvm-project.git/commit/?id=125af5686765f915abcdcca60ad255fda95667d2'/>
<id>125af5686765f915abcdcca60ad255fda95667d2</id>
<content type='text'>
For flat memory instructions where the address is supplied as a base address
register with an immediate offset, the memory aperture test ignores the
immediate offset. Currently, SDISel does not respect that, which leads to
miscompilations where valid input programs crash when the address computation
relies on the immediate offset to get the base address in the proper memory
aperture. Global or scratch instructions are not affected.

This patch only selects flat instructions with immediate offsets from PTRADD
address computations with the inbounds flag: If the PTRADD does not leave the
bounds of the allocated object, it cannot leave the bounds of the memory
aperture and is therefore safe to handle with an immediate offset.

Affected tests:

- CodeGen/AMDGPU/fold-gep-offset.ll: Offsets are no longer wrongly folded, added
  new positive tests where we still do fold them.
- CodeGen/AMDGPU/infer-addrspace-flat-atomic.ll: Offset folding doesn't seem
  integral to this test, so the test is not changed to make offset folding still
  happen.
- CodeGen/AMDGPU/loop-prefetch-data.ll: loop-reduce transforms inbounds
  addresses for accesses to be based on potentially OOB addresses used for
  prefetching.
- I think the remaining ones suffer from the limited preservation of the
  inbounds flag in PTRADD DAGCombines due to the provenance problems pointed out
  in PR #165424 and the fact that
  `AMDGPUTargetLowering::SplitVector{Load|Store}` legalizes too-wide accesses by
  repeatedly splitting them in half.  Legalizing a V32S32 memory accesses
  therefore leads to inbounds ptradd chains like (ptradd inbounds (ptradd
  inbounds (ptradd inbounds P, 64), 32), 16). The DAGCombines fold them into a
  single ptradd, but the involved transformations generally cannot preserve the
  inbounds flag (even though it would be valid in this case).

Similar previous PR that relied on `ISD::ADD inbounds` instead of `ISD::PTRADD inbounds` (closed): #132353
Analogous PR for GISel (merged): #153001

Fixes SWDEV-516125.</content>
<content type='xhtml'>
<div xmlns='http://www.w3.org/1999/xhtml'>
<pre>
For flat memory instructions where the address is supplied as a base address
register with an immediate offset, the memory aperture test ignores the
immediate offset. Currently, SDISel does not respect that, which leads to
miscompilations where valid input programs crash when the address computation
relies on the immediate offset to get the base address in the proper memory
aperture. Global or scratch instructions are not affected.

This patch only selects flat instructions with immediate offsets from PTRADD
address computations with the inbounds flag: If the PTRADD does not leave the
bounds of the allocated object, it cannot leave the bounds of the memory
aperture and is therefore safe to handle with an immediate offset.

Affected tests:

- CodeGen/AMDGPU/fold-gep-offset.ll: Offsets are no longer wrongly folded, added
  new positive tests where we still do fold them.
- CodeGen/AMDGPU/infer-addrspace-flat-atomic.ll: Offset folding doesn't seem
  integral to this test, so the test is not changed to make offset folding still
  happen.
- CodeGen/AMDGPU/loop-prefetch-data.ll: loop-reduce transforms inbounds
  addresses for accesses to be based on potentially OOB addresses used for
  prefetching.
- I think the remaining ones suffer from the limited preservation of the
  inbounds flag in PTRADD DAGCombines due to the provenance problems pointed out
  in PR #165424 and the fact that
  `AMDGPUTargetLowering::SplitVector{Load|Store}` legalizes too-wide accesses by
  repeatedly splitting them in half.  Legalizing a V32S32 memory accesses
  therefore leads to inbounds ptradd chains like (ptradd inbounds (ptradd
  inbounds (ptradd inbounds P, 64), 32), 16). The DAGCombines fold them into a
  single ptradd, but the involved transformations generally cannot preserve the
  inbounds flag (even though it would be valid in this case).

Similar previous PR that relied on `ISD::ADD inbounds` instead of `ISD::PTRADD inbounds` (closed): #132353
Analogous PR for GISel (merged): #153001

Fixes SWDEV-516125.</pre>
</div>
</content>
</entry>
<entry>
<title>[AMDGPU] Enable XNACK on gfx1250 (#161457)</title>
<updated>2025-10-03T15:04:55+00:00</updated>
<author>
<name>Shilei Tian</name>
<email>i@tianshilei.me</email>
</author>
<published>2025-10-03T15:04:55+00:00</published>
<link rel='alternate' type='text/html' href='https://git.belthelziquor.com/llvm-project.git/commit/?id=e7f47e70e75512aa73116fbafaf09dfb2b881672'/>
<id>e7f47e70e75512aa73116fbafaf09dfb2b881672</id>
<content type='text'>
This should be always on.

Fixes SWDEV-555931.</content>
<content type='xhtml'>
<div xmlns='http://www.w3.org/1999/xhtml'>
<pre>
This should be always on.

Fixes SWDEV-555931.</pre>
</div>
</content>
</entry>
<entry>
<title>[AMDGPU][SDAG] Enable ISD::PTRADD for 64-bit AS by default (#146076)</title>
<updated>2025-10-02T08:06:25+00:00</updated>
<author>
<name>Fabian Ritter</name>
<email>fabian.ritter@amd.com</email>
</author>
<published>2025-10-02T08:06:25+00:00</published>
<link rel='alternate' type='text/html' href='https://git.belthelziquor.com/llvm-project.git/commit/?id=bf847a8b9d54643c457eaaad7f5dc60e6454cd2e'/>
<id>bf847a8b9d54643c457eaaad7f5dc60e6454cd2e</id>
<content type='text'>
Also removes the command line option to control this feature.

There seem to be mainly two kinds of test changes:
- Some operands of addition instructions are swapped; that is to be expected
  since PTRADD is not commutative.
- Improvements in code generation, probably because the legacy lowering enabled
  some transformations that were sometimes harmful.

For SWDEV-516125.</content>
<content type='xhtml'>
<div xmlns='http://www.w3.org/1999/xhtml'>
<pre>
Also removes the command line option to control this feature.

There seem to be mainly two kinds of test changes:
- Some operands of addition instructions are swapped; that is to be expected
  since PTRADD is not commutative.
- Improvements in code generation, probably because the legacy lowering enabled
  some transformations that were sometimes harmful.

For SWDEV-516125.</pre>
</div>
</content>
</entry>
<entry>
<title>[AMDGPU][gfx1250] Remove SCOPE_SE for scratch stores (#157640)</title>
<updated>2025-09-10T09:03:58+00:00</updated>
<author>
<name>Pierre van Houtryve</name>
<email>pierre.vanhoutryve@amd.com</email>
</author>
<published>2025-09-10T09:03:58+00:00</published>
<link rel='alternate' type='text/html' href='https://git.belthelziquor.com/llvm-project.git/commit/?id=d6d0f4f156e27e5171475d229b8ea2616c2b3d0c'/>
<id>d6d0f4f156e27e5171475d229b8ea2616c2b3d0c</id>
<content type='text'>
</content>
<content type='xhtml'>
<div xmlns='http://www.w3.org/1999/xhtml'>
<pre>
</pre>
</div>
</content>
</entry>
<entry>
<title>[LICM] Do not reassociate constant offset GEP (#151492)</title>
<updated>2025-08-01T07:43:15+00:00</updated>
<author>
<name>Nikita Popov</name>
<email>npopov@redhat.com</email>
</author>
<published>2025-08-01T07:43:15+00:00</published>
<link rel='alternate' type='text/html' href='https://git.belthelziquor.com/llvm-project.git/commit/?id=0a41e7c87ef910d0124c50354422f3b5290518e9'/>
<id>0a41e7c87ef910d0124c50354422f3b5290518e9</id>
<content type='text'>
LICM tries to reassociate GEPs in order to hoist an invariant GEP.
Currently, it also does this in the case where the GEP has a constant
offset.

This is usually undesirable. From a back-end perspective, constant GEPs
are usually free because they can be folded into addressing modes, so
this just increases register pressume. From a middle-end perspective,
keeping constant offsets last in the chain makes it easier to analyze
the relationship between multiple GEPs on the same base, especially
after CSE.

The worst that can happen here is if we start with something like

```
loop {
   p + 4*x
   p + 4*x + 1
   p + 4*x + 2
   p + 4*x + 3
}
```

And LICM converts it into:

```
p.1 = p + 1
p.2 = p + 2
p.3 = p + 3
loop {
   p + 4*x
   p.1 + 4*x
   p.2 + 4*x
   p.3 + 4*x
}
```

Which is much worse than leaving it for CSE to convert to:
```
loop {
   p2 = p + 4*x
   p2 + 1
   p2 + 2
   p2 + 3
}
```</content>
<content type='xhtml'>
<div xmlns='http://www.w3.org/1999/xhtml'>
<pre>
LICM tries to reassociate GEPs in order to hoist an invariant GEP.
Currently, it also does this in the case where the GEP has a constant
offset.

This is usually undesirable. From a back-end perspective, constant GEPs
are usually free because they can be folded into addressing modes, so
this just increases register pressume. From a middle-end perspective,
keeping constant offsets last in the chain makes it easier to analyze
the relationship between multiple GEPs on the same base, especially
after CSE.

The worst that can happen here is if we start with something like

```
loop {
   p + 4*x
   p + 4*x + 1
   p + 4*x + 2
   p + 4*x + 3
}
```

And LICM converts it into:

```
p.1 = p + 1
p.2 = p + 2
p.3 = p + 3
loop {
   p + 4*x
   p.1 + 4*x
   p.2 + 4*x
   p.3 + 4*x
}
```

Which is much worse than leaving it for CSE to convert to:
```
loop {
   p2 = p + 4*x
   p2 + 1
   p2 + 2
   p2 + 3
}
```</pre>
</div>
</content>
</entry>
<entry>
<title>[AMDGPU] Regenerate test checks (NFC)</title>
<updated>2025-07-31T15:02:48+00:00</updated>
<author>
<name>Nikita Popov</name>
<email>npopov@redhat.com</email>
</author>
<published>2025-07-31T15:02:10+00:00</published>
<link rel='alternate' type='text/html' href='https://git.belthelziquor.com/llvm-project.git/commit/?id=e2bd92e56b98b15595f2d36a17aad2fe419bd39c'/>
<id>e2bd92e56b98b15595f2d36a17aad2fe419bd39c</id>
<content type='text'>
</content>
<content type='xhtml'>
<div xmlns='http://www.w3.org/1999/xhtml'>
<pre>
</pre>
</div>
</content>
</entry>
<entry>
<title>[AMDGPU] Select VMEM prefetch for llvm.prefetch on gfx1250 (#150493)</title>
<updated>2025-07-24T20:22:50+00:00</updated>
<author>
<name>Stanislav Mekhanoshin</name>
<email>Stanislav.Mekhanoshin@amd.com</email>
</author>
<published>2025-07-24T20:22:50+00:00</published>
<link rel='alternate' type='text/html' href='https://git.belthelziquor.com/llvm-project.git/commit/?id=96e5eed92af267b151c29a95f2c208f2bc0a32b3'/>
<id>96e5eed92af267b151c29a95f2c208f2bc0a32b3</id>
<content type='text'>
We have a choice to use a scalar or vector prefetch for an uniform
pointer. Since we do not have scalar stores our scalar cache is
practically readonly. The rw argument of the prefetch intrinsic is
used to force vector operation even for an uniform case. On GFX12
scalar prefetch will be used anyway, it is still useful but it will
only bring data to L2.</content>
<content type='xhtml'>
<div xmlns='http://www.w3.org/1999/xhtml'>
<pre>
We have a choice to use a scalar or vector prefetch for an uniform
pointer. Since we do not have scalar stores our scalar cache is
practically readonly. The rw argument of the prefetch intrinsic is
used to force vector operation even for an uniform case. On GFX12
scalar prefetch will be used anyway, it is still useful but it will
only bring data to L2.</pre>
</div>
</content>
</entry>
<entry>
<title>[AMDGPU] Add safe-smem-prefetch SubtargetFeature off by default (#130050)</title>
<updated>2025-03-07T10:10:21+00:00</updated>
<author>
<name>Mariusz Sikora</name>
<email>mariusz.sikora@amd.com</email>
</author>
<published>2025-03-07T10:10:21+00:00</published>
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<id>e9de91e989de2b61ded7f471b48453eddf77ca29</id>
<content type='text'>
S_PREFETCH_* instructions may cause host to terminate process in case of
the invalid address.

Co-authored-by: Stanislav Mekhanoshin &lt;Stanislav.Mekhanoshin@amd.com&gt;</content>
<content type='xhtml'>
<div xmlns='http://www.w3.org/1999/xhtml'>
<pre>
S_PREFETCH_* instructions may cause host to terminate process in case of
the invalid address.

Co-authored-by: Stanislav Mekhanoshin &lt;Stanislav.Mekhanoshin@amd.com&gt;</pre>
</div>
</content>
</entry>
<entry>
<title>Reapply "[AMDGPU] Still set up the two SGPRs for queue ptr even it is COV5 (#112403)"</title>
<updated>2024-11-09T01:21:16+00:00</updated>
<author>
<name>Shilei Tian</name>
<email>i@tianshilei.me</email>
</author>
<published>2024-11-09T01:21:16+00:00</published>
<link rel='alternate' type='text/html' href='https://git.belthelziquor.com/llvm-project.git/commit/?id=6548b6354d1d990e1c98736f5e7c3de876bedc8e'/>
<id>6548b6354d1d990e1c98736f5e7c3de876bedc8e</id>
<content type='text'>
This reverts commit ca33649abe5fad93c57afef54e43ed9b3249cd86.
</content>
<content type='xhtml'>
<div xmlns='http://www.w3.org/1999/xhtml'>
<pre>
This reverts commit ca33649abe5fad93c57afef54e43ed9b3249cd86.
</pre>
</div>
</content>
</entry>
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