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<title>llvm-project.git/llvm/test/CodeGen/AMDGPU/local-atomicrmw-fsub.ll, branch main</title>
<subtitle>Unnamed repository; edit this file 'description' to name the repository.
</subtitle>
<link rel='alternate' type='text/html' href='https://git.belthelziquor.com/llvm-project.git/'/>
<entry>
<title>Revert "[RegAlloc] Fix the terminal rule check for interfere with DstReg (#168661)"</title>
<updated>2025-11-23T05:17:45+00:00</updated>
<author>
<name>Aiden Grossman</name>
<email>aidengrossman@google.com</email>
</author>
<published>2025-11-23T05:17:45+00:00</published>
<link rel='alternate' type='text/html' href='https://git.belthelziquor.com/llvm-project.git/commit/?id=d5f3ab8ec97786476a077b0c8e35c7c337dfddf2'/>
<id>d5f3ab8ec97786476a077b0c8e35c7c337dfddf2</id>
<content type='text'>
This reverts commit 0859ac5866a0228f5607dd329f83f4a9622dedcc.

This caused a couple test failures, likely due to a mid-air collision.
Reverting for now to get the tree back to green and allow the original
author to run UTC/friends and verify the output.
</content>
<content type='xhtml'>
<div xmlns='http://www.w3.org/1999/xhtml'>
<pre>
This reverts commit 0859ac5866a0228f5607dd329f83f4a9622dedcc.

This caused a couple test failures, likely due to a mid-air collision.
Reverting for now to get the tree back to green and allow the original
author to run UTC/friends and verify the output.
</pre>
</div>
</content>
</entry>
<entry>
<title>[RegAlloc] Fix the terminal rule check for interfere with DstReg (#168661)</title>
<updated>2025-11-23T02:11:24+00:00</updated>
<author>
<name>hstk30-hw</name>
<email>hanwei62@huawei.com</email>
</author>
<published>2025-11-23T02:11:24+00:00</published>
<link rel='alternate' type='text/html' href='https://git.belthelziquor.com/llvm-project.git/commit/?id=0859ac5866a0228f5607dd329f83f4a9622dedcc'/>
<id>0859ac5866a0228f5607dd329f83f4a9622dedcc</id>
<content type='text'>
This maybe a bug which is introduced by commit
6749ae36b4a33769e7a77cf812d7cd0a908ae3b9, and has been present ever
since.
In this case, `OtherReg` always overlaps with `DstReg` cause they from
the `Copy` all.</content>
<content type='xhtml'>
<div xmlns='http://www.w3.org/1999/xhtml'>
<pre>
This maybe a bug which is introduced by commit
6749ae36b4a33769e7a77cf812d7cd0a908ae3b9, and has been present ever
since.
In this case, `OtherReg` always overlaps with `DstReg` cause they from
the `Copy` all.</pre>
</div>
</content>
</entry>
<entry>
<title>RegisterCoalescer: Enable terminal rule by default for AMDGPU (#161621)</title>
<updated>2025-11-10T17:37:14+00:00</updated>
<author>
<name>Matt Arsenault</name>
<email>Matthew.Arsenault@amd.com</email>
</author>
<published>2025-11-10T17:37:14+00:00</published>
<link rel='alternate' type='text/html' href='https://git.belthelziquor.com/llvm-project.git/commit/?id=e95f6fa123de1ef8654a2f494cfd743146f94a25'/>
<id>e95f6fa123de1ef8654a2f494cfd743146f94a25</id>
<content type='text'>
Introduce a target hook to incrementally flip the behavior of
targets with test changes, and start by implementing it for AMDGPU.

This appears to be forgotten switch flip from 2015. This
seems to do a nicer job with subregister copies. Most of the
test changes are improvements or neutral, not that many are
light regressions. The worst AMDGPU regressions are for true16
in the atomic tests, but I think that's due to existing true16
issues.</content>
<content type='xhtml'>
<div xmlns='http://www.w3.org/1999/xhtml'>
<pre>
Introduce a target hook to incrementally flip the behavior of
targets with test changes, and start by implementing it for AMDGPU.

This appears to be forgotten switch flip from 2015. This
seems to do a nicer job with subregister copies. Most of the
test changes are improvements or neutral, not that many are
light regressions. The worst AMDGPU regressions are for true16
in the atomic tests, but I think that's due to existing true16
issues.</pre>
</div>
</content>
</entry>
<entry>
<title>[AMDGPU][True16][Codegen] remove another build_vector pattern from true16 (#149861)</title>
<updated>2025-09-04T22:08:18+00:00</updated>
<author>
<name>Brox Chen</name>
<email>guochen2@amd.com</email>
</author>
<published>2025-09-04T22:08:18+00:00</published>
<link rel='alternate' type='text/html' href='https://git.belthelziquor.com/llvm-project.git/commit/?id=dfdfc4e490f211155ffd581ea0ba8458e4290db6'/>
<id>dfdfc4e490f211155ffd581ea0ba8458e4290db6</id>
<content type='text'>
Remove another build_vector pattern which takes a i16 but placed in a
VGPR_32 from true16 mode. This stop isel from generating illegal
"vgpr_32 = COPY vgpr_16".

ISel will use vgpr16 build vector pattern in true16 mode instead</content>
<content type='xhtml'>
<div xmlns='http://www.w3.org/1999/xhtml'>
<pre>
Remove another build_vector pattern which takes a i16 but placed in a
VGPR_32 from true16 mode. This stop isel from generating illegal
"vgpr_32 = COPY vgpr_16".

ISel will use vgpr16 build vector pattern in true16 mode instead</pre>
</div>
</content>
</entry>
<entry>
<title>[AMDGPU][True16][CodeGen] use vgpr16 for zext patterns (reopen #153894) (#154211)</title>
<updated>2025-08-20T14:26:49+00:00</updated>
<author>
<name>Brox Chen</name>
<email>guochen2@amd.com</email>
</author>
<published>2025-08-20T14:26:49+00:00</published>
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<id>c50ed05cada308dea282e026cc782a9ea3ab0c29</id>
<content type='text'>
recreate this patch from
https://github.com/llvm/llvm-project/pull/153894

It seems ISel sliently ignore the `i64 = zext i16` with a chained
`reg_sequence` pattern and thus this is causing a selection failure in
hip test. Recreate a new patch with an alternative pattern, and added a
ll test global-extload-gfx11plus.ll</content>
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<div xmlns='http://www.w3.org/1999/xhtml'>
<pre>
recreate this patch from
https://github.com/llvm/llvm-project/pull/153894

It seems ISel sliently ignore the `i64 = zext i16` with a chained
`reg_sequence` pattern and thus this is causing a selection failure in
hip test. Recreate a new patch with an alternative pattern, and added a
ll test global-extload-gfx11plus.ll</pre>
</div>
</content>
</entry>
<entry>
<title>Revert "[AMDGPU][True16][CodeGen] use vgpr16 for zext patterns (#1538… (#154163)</title>
<updated>2025-08-18T18:01:19+00:00</updated>
<author>
<name>Brox Chen</name>
<email>guochen2@amd.com</email>
</author>
<published>2025-08-18T18:01:19+00:00</published>
<link rel='alternate' type='text/html' href='https://git.belthelziquor.com/llvm-project.git/commit/?id=d49aab10bd424f67a0df0d70f653f8deeb498a16'/>
<id>d49aab10bd424f67a0df0d70f653f8deeb498a16</id>
<content type='text'>
This reverts commit 7c53c6162bd43d952546a3ef7d019babd5244c29.

This patch hit an issue in hip test. revert and will reopen later</content>
<content type='xhtml'>
<div xmlns='http://www.w3.org/1999/xhtml'>
<pre>
This reverts commit 7c53c6162bd43d952546a3ef7d019babd5244c29.

This patch hit an issue in hip test. revert and will reopen later</pre>
</div>
</content>
</entry>
<entry>
<title>[AMDGPU][True16][CodeGen] use vgpr16 for zext patterns (#153894)</title>
<updated>2025-08-18T15:01:57+00:00</updated>
<author>
<name>Brox Chen</name>
<email>guochen2@amd.com</email>
</author>
<published>2025-08-18T15:01:57+00:00</published>
<link rel='alternate' type='text/html' href='https://git.belthelziquor.com/llvm-project.git/commit/?id=7c53c6162bd43d952546a3ef7d019babd5244c29'/>
<id>7c53c6162bd43d952546a3ef7d019babd5244c29</id>
<content type='text'>
Update true16 mode with zext patterns using vgpr16 for 16bit data types.
This stop isel from inserting invalid "vgpr32 = copy vgpr16"</content>
<content type='xhtml'>
<div xmlns='http://www.w3.org/1999/xhtml'>
<pre>
Update true16 mode with zext patterns using vgpr16 for 16bit data types.
This stop isel from inserting invalid "vgpr32 = copy vgpr16"</pre>
</div>
</content>
</entry>
<entry>
<title>[AMDGPU] Fix bad removal of s_delay_alu (#145728)</title>
<updated>2025-06-27T14:15:10+00:00</updated>
<author>
<name>Ana Mihajlovic</name>
<email>Ana.Mihajlovic@amd.com</email>
</author>
<published>2025-06-27T14:15:10+00:00</published>
<link rel='alternate' type='text/html' href='https://git.belthelziquor.com/llvm-project.git/commit/?id=08d747c1ef659074549def24a9e92d6604e08e61'/>
<id>08d747c1ef659074549def24a9e92d6604e08e61</id>
<content type='text'>
instructionWaitsForSGPRWrites function covers ALL SALU instructions,
including those like s_waitcnt that don't read from sgpr. This results
in removing delay_alu instructions in cases like VALU-&gt;SGPR-&gt;VALU, which
results in performance regression. Change modifies the function so that
it checks if instruction also reads a sgpr.</content>
<content type='xhtml'>
<div xmlns='http://www.w3.org/1999/xhtml'>
<pre>
instructionWaitsForSGPRWrites function covers ALL SALU instructions,
including those like s_waitcnt that don't read from sgpr. This results
in removing delay_alu instructions in cases like VALU-&gt;SGPR-&gt;VALU, which
results in performance regression. Change modifies the function so that
it checks if instruction also reads a sgpr.</pre>
</div>
</content>
</entry>
<entry>
<title>[AMDGPU][True16][CodeGen] update more GFX11Plus codegen test with true16 mode (#138600)</title>
<updated>2025-05-12T16:19:46+00:00</updated>
<author>
<name>Brox Chen</name>
<email>guochen2@amd.com</email>
</author>
<published>2025-05-12T16:19:46+00:00</published>
<link rel='alternate' type='text/html' href='https://git.belthelziquor.com/llvm-project.git/commit/?id=89f82673406cf9b4877d6eab7fa80940b39479e9'/>
<id>89f82673406cf9b4877d6eab7fa80940b39479e9</id>
<content type='text'>
This is a NFC patch.

This patch duplicate GFX11plus runlines and apply them with
"+mattr=+real-true16" and "+mattr=-real-true16" on more gfx11/gfx12
tests. And then update the test with the update script</content>
<content type='xhtml'>
<div xmlns='http://www.w3.org/1999/xhtml'>
<pre>
This is a NFC patch.

This patch duplicate GFX11plus runlines and apply them with
"+mattr=+real-true16" and "+mattr=-real-true16" on more gfx11/gfx12
tests. And then update the test with the update script</pre>
</div>
</content>
</entry>
<entry>
<title>[AMDGPU][InsertWaitCnts] Track global_wb/inv/wbinv (#135340)</title>
<updated>2025-04-22T12:53:55+00:00</updated>
<author>
<name>Pierre van Houtryve</name>
<email>pierre.vanhoutryve@amd.com</email>
</author>
<published>2025-04-22T12:53:55+00:00</published>
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<id>ec3a90509d7db3b32d6102351c86470d9799dc9b</id>
<content type='text'>
wb/wbinv use storecnt, inv uses loadcnt.
Track them as VMEM_WRITE_ACCESS and VMEM_READ_ACCESS to avoid
InsertWaitCnt incorrectly eliminating the waitcnts after these instructions.

Solves SWDEV-526604</content>
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<pre>
wb/wbinv use storecnt, inv uses loadcnt.
Track them as VMEM_WRITE_ACCESS and VMEM_READ_ACCESS to avoid
InsertWaitCnt incorrectly eliminating the waitcnts after these instructions.

Solves SWDEV-526604</pre>
</div>
</content>
</entry>
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