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<title>llvm-project.git/llvm/test/CodeGen/AMDGPU/llvm.mulo.ll, branch users/nico/python-2</title>
<subtitle>Unnamed repository; edit this file 'description' to name the repository.
</subtitle>
<link rel='alternate' type='text/html' href='https://git.belthelziquor.com/llvm-project.git/'/>
<entry>
<title>[AMDGPU] Fix bad removal of s_delay_alu (#145728)</title>
<updated>2025-06-27T14:15:10+00:00</updated>
<author>
<name>Ana Mihajlovic</name>
<email>Ana.Mihajlovic@amd.com</email>
</author>
<published>2025-06-27T14:15:10+00:00</published>
<link rel='alternate' type='text/html' href='https://git.belthelziquor.com/llvm-project.git/commit/?id=08d747c1ef659074549def24a9e92d6604e08e61'/>
<id>08d747c1ef659074549def24a9e92d6604e08e61</id>
<content type='text'>
instructionWaitsForSGPRWrites function covers ALL SALU instructions,
including those like s_waitcnt that don't read from sgpr. This results
in removing delay_alu instructions in cases like VALU-&gt;SGPR-&gt;VALU, which
results in performance regression. Change modifies the function so that
it checks if instruction also reads a sgpr.</content>
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<pre>
instructionWaitsForSGPRWrites function covers ALL SALU instructions,
including those like s_waitcnt that don't read from sgpr. This results
in removing delay_alu instructions in cases like VALU-&gt;SGPR-&gt;VALU, which
results in performance regression. Change modifies the function so that
it checks if instruction also reads a sgpr.</pre>
</div>
</content>
</entry>
<entry>
<title>Reapply [AMDGPU] SIFixSgprCopies should not process twice VGPR to SGPR copies inserted by PHI preprocessing. (#135243)</title>
<updated>2025-04-10T20:18:21+00:00</updated>
<author>
<name>alex-t</name>
<email>alex-t@users.noreply.github.com</email>
</author>
<published>2025-04-10T20:18:21+00:00</published>
<link rel='alternate' type='text/html' href='https://git.belthelziquor.com/llvm-project.git/commit/?id=edd7b559c09e8e9b1fd0fc1905f0aaa67c74331f'/>
<id>edd7b559c09e8e9b1fd0fc1905f0aaa67c74331f</id>
<content type='text'>
LIT tests which were incorrectly merged are corrected.</content>
<content type='xhtml'>
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<pre>
LIT tests which were incorrectly merged are corrected.</pre>
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</content>
</entry>
<entry>
<title>Revert "[AMDGPU] SIFixSgprCopies should not process twice VGPR to SGPR copies inserted by PHI preprocessing. (#134153)"</title>
<updated>2025-04-10T17:20:01+00:00</updated>
<author>
<name>Nico Weber</name>
<email>thakis@chromium.org</email>
</author>
<published>2025-04-10T17:20:01+00:00</published>
<link rel='alternate' type='text/html' href='https://git.belthelziquor.com/llvm-project.git/commit/?id=464035fc7de52b6fe9b09c9f4c9a19fd5d46fcae'/>
<id>464035fc7de52b6fe9b09c9f4c9a19fd5d46fcae</id>
<content type='text'>
This reverts commit 0563569978fee1e780a560494c89869074933f58.

Breaks tests, see comments on https://github.com/llvm/llvm-project/pull/134153
</content>
<content type='xhtml'>
<div xmlns='http://www.w3.org/1999/xhtml'>
<pre>
This reverts commit 0563569978fee1e780a560494c89869074933f58.

Breaks tests, see comments on https://github.com/llvm/llvm-project/pull/134153
</pre>
</div>
</content>
</entry>
<entry>
<title>[AMDGPU] SIFixSgprCopies should not process twice VGPR to SGPR copies inserted by PHI preprocessing. (#134153)</title>
<updated>2025-04-10T16:30:52+00:00</updated>
<author>
<name>alex-t</name>
<email>alex-t@users.noreply.github.com</email>
</author>
<published>2025-04-10T16:30:52+00:00</published>
<link rel='alternate' type='text/html' href='https://git.belthelziquor.com/llvm-project.git/commit/?id=0563569978fee1e780a560494c89869074933f58'/>
<id>0563569978fee1e780a560494c89869074933f58</id>
<content type='text'>
PHI operands and results must belong to the same register class.
If a PHI node produces an SGPR, but one of its operands is a VGPR, we
insert a VGPR-to-SGPR copy in the operand’s source block. The PHI
operand is then updated to use the destination register of the inserted
copy.

These inserted copies are processed immediately when they are created.
Therefore, we should avoid reprocessing them when handling their parent
block later.

---------

Co-authored-by: Matt Arsenault &lt;arsenm2@gmail.com&gt;</content>
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<pre>
PHI operands and results must belong to the same register class.
If a PHI node produces an SGPR, but one of its operands is a VGPR, we
insert a VGPR-to-SGPR copy in the operand’s source block. The PHI
operand is then updated to use the destination register of the inserted
copy.

These inserted copies are processed immediately when they are created.
Therefore, we should avoid reprocessing them when handling their parent
block later.

---------

Co-authored-by: Matt Arsenault &lt;arsenm2@gmail.com&gt;</pre>
</div>
</content>
</entry>
<entry>
<title>[AMDGPU] Unused sdst writing to null (#133229)</title>
<updated>2025-03-28T17:12:34+00:00</updated>
<author>
<name>Ana Mihajlovic</name>
<email>Ana.Mihajlovic@amd.com</email>
</author>
<published>2025-03-28T17:12:34+00:00</published>
<link rel='alternate' type='text/html' href='https://git.belthelziquor.com/llvm-project.git/commit/?id=8c7550132f410766598ba88de6b7e7a2a4607f67'/>
<id>8c7550132f410766598ba88de6b7e7a2a4607f67</id>
<content type='text'>
Unused sdst writing to null to avoid a false VALU-&gt;SALU dependency
stall. This requires using the VOP3 encoding.</content>
<content type='xhtml'>
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<pre>
Unused sdst writing to null to avoid a false VALU-&gt;SALU dependency
stall. This requires using the VOP3 encoding.</pre>
</div>
</content>
</entry>
<entry>
<title>AMDGPU: Move insertion into V2SCopies map (#130776)</title>
<updated>2025-03-18T16:28:49+00:00</updated>
<author>
<name>Matt Arsenault</name>
<email>Matthew.Arsenault@amd.com</email>
</author>
<published>2025-03-18T16:28:49+00:00</published>
<link rel='alternate' type='text/html' href='https://git.belthelziquor.com/llvm-project.git/commit/?id=dea5aa73fa1984eddde14308803bdfca56f2bc14'/>
<id>dea5aa73fa1984eddde14308803bdfca56f2bc14</id>
<content type='text'>
Insert the start instruction directly into the map before the uses. This
prevents improperly re-visting sgpr-&gt;vgpr phi inputs multiple times
which
would trigger a use after free.

I don't particularly trust the iteration scheme here. This is also
unnecessarily revisting transitive users of a phi or reg_sequence for
every
input operand, but I will address that separately.

Fixes #130646. I also believe it fixes #130119, although that test fails
less consistently for me.</content>
<content type='xhtml'>
<div xmlns='http://www.w3.org/1999/xhtml'>
<pre>
Insert the start instruction directly into the map before the uses. This
prevents improperly re-visting sgpr-&gt;vgpr phi inputs multiple times
which
would trigger a use after free.

I don't particularly trust the iteration scheme here. This is also
unnecessarily revisting transitive users of a phi or reg_sequence for
every
input operand, but I will address that separately.

Fixes #130646. I also believe it fixes #130119, although that test fails
less consistently for me.</pre>
</div>
</content>
</entry>
<entry>
<title>Reland "[AMDGPU] Remove s_delay_alu for VALU-&gt;SGPR-&gt;SALU (#127212)" (#131111)</title>
<updated>2025-03-13T09:26:20+00:00</updated>
<author>
<name>Ana Mihajlovic</name>
<email>Ana.Mihajlovic@amd.com</email>
</author>
<published>2025-03-13T09:26:20+00:00</published>
<link rel='alternate' type='text/html' href='https://git.belthelziquor.com/llvm-project.git/commit/?id=459b4e3fe10805b110bc89aa857532715bfe54e0'/>
<id>459b4e3fe10805b110bc89aa857532715bfe54e0</id>
<content type='text'>
We have a VALU-&gt;SGPR-&gt;SALU (VALU writing to SGPR and SALU reading from
it). When VALU is issued, it increments internal counter VA_SDST used to
track use of this SGPR. SALU will not issue until VA_SDST is zero, that
is when VALU is finished writing. Therefore, delays added by s_delay_alu
are not needed in this situation.</content>
<content type='xhtml'>
<div xmlns='http://www.w3.org/1999/xhtml'>
<pre>
We have a VALU-&gt;SGPR-&gt;SALU (VALU writing to SGPR and SALU reading from
it). When VALU is issued, it increments internal counter VA_SDST used to
track use of this SGPR. SALU will not issue until VA_SDST is zero, that
is when VALU is finished writing. Therefore, delays added by s_delay_alu
are not needed in this situation.</pre>
</div>
</content>
</entry>
<entry>
<title>AMDGPU: Replace ptr addrspace(1) undefs with poison (#130900)</title>
<updated>2025-03-13T01:25:02+00:00</updated>
<author>
<name>Matt Arsenault</name>
<email>Matthew.Arsenault@amd.com</email>
</author>
<published>2025-03-13T01:25:02+00:00</published>
<link rel='alternate' type='text/html' href='https://git.belthelziquor.com/llvm-project.git/commit/?id=6705d812b8563ae02cad3f7125de7193c0128c20'/>
<id>6705d812b8563ae02cad3f7125de7193c0128c20</id>
<content type='text'>
Many tests use store to undef as a placeholder use, so just replace
all of these with poison.</content>
<content type='xhtml'>
<div xmlns='http://www.w3.org/1999/xhtml'>
<pre>
Many tests use store to undef as a placeholder use, so just replace
all of these with poison.</pre>
</div>
</content>
</entry>
<entry>
<title>Revert "[AMDGPU] Remove s_delay_alu for VALU-&gt;SGPR-&gt;SALU (#127212)"</title>
<updated>2025-03-12T19:09:09+00:00</updated>
<author>
<name>Kazu Hirata</name>
<email>kazu@google.com</email>
</author>
<published>2025-03-12T19:09:09+00:00</published>
<link rel='alternate' type='text/html' href='https://git.belthelziquor.com/llvm-project.git/commit/?id=aa008e00085a260b2ed130b3430cc4640144ab30'/>
<id>aa008e00085a260b2ed130b3430cc4640144ab30</id>
<content type='text'>
This reverts commit 71582c6667a6334c688734cae628e906b3c1ac1d.

Multiple buildbot failures have been reported:
https://github.com/llvm/llvm-project/pull/127212
</content>
<content type='xhtml'>
<div xmlns='http://www.w3.org/1999/xhtml'>
<pre>
This reverts commit 71582c6667a6334c688734cae628e906b3c1ac1d.

Multiple buildbot failures have been reported:
https://github.com/llvm/llvm-project/pull/127212
</pre>
</div>
</content>
</entry>
<entry>
<title>[AMDGPU] Remove s_delay_alu for VALU-&gt;SGPR-&gt;SALU (#127212)</title>
<updated>2025-03-12T16:33:07+00:00</updated>
<author>
<name>Ana Mihajlovic</name>
<email>Ana.Mihajlovic@amd.com</email>
</author>
<published>2025-03-12T16:33:07+00:00</published>
<link rel='alternate' type='text/html' href='https://git.belthelziquor.com/llvm-project.git/commit/?id=71582c6667a6334c688734cae628e906b3c1ac1d'/>
<id>71582c6667a6334c688734cae628e906b3c1ac1d</id>
<content type='text'>
We have a VALU-&gt;SGPR-&gt;SALU (VALU writing to SGPR and SALU reading from
it). When VALU is issued, it increments internal counter VA_SDST used to
track use of this SGPR. SALU will not issue until VA_SDST is zero, that
is when VALU is finished writing. Therefore, delays added by s_delay_alu
are not needed in this situation.</content>
<content type='xhtml'>
<div xmlns='http://www.w3.org/1999/xhtml'>
<pre>
We have a VALU-&gt;SGPR-&gt;SALU (VALU writing to SGPR and SALU reading from
it). When VALU is issued, it increments internal counter VA_SDST used to
track use of this SGPR. SALU will not issue until VA_SDST is zero, that
is when VALU is finished writing. Therefore, delays added by s_delay_alu
are not needed in this situation.</pre>
</div>
</content>
</entry>
</feed>
