llvm-project.git/llvm/test/CodeGen/AMDGPU/llvm.frexp.ll, branch users/mingmingl-llvm/samplefdo-profile-format Unnamed repository; edit this file 'description' to name the repository. AMDGPU: Allow folding multiple uses of some immediates into copies (#154757) 2025-09-05T23:22:09+00:00 Matt Arsenault Matthew.Arsenault@amd.com 2025-09-05T23:22:09+00:00 884130bf9309872d3d472d984a3c3bb90f454083 In some cases this will require an avoidable re-defining of a register, but it works out better most of the time. Also allow folding 64-bit immediates into subregister extracts, unless it would break an inline constant. We could be more aggressive here, but this set of conditions seems to do a reasonable job without introducing too many regressions. 
In some cases this will require an avoidable re-defining of
a register, but it works out better most of the time. Also allow
folding 64-bit immediates into subregister extracts, unless it would
break an inline constant.

We could be more aggressive here, but this set of conditions seems
to do a reasonable job without introducing too many regressions.
 Add FABS to canCreateUndefOrPoison (#149440) 2025-07-18T06:17:15+00:00 Shoreshen 372660931@qq.com 2025-07-18T06:17:15+00:00 5fe9b5235298dc67864e947ea23df201aec177fc FABS will not create undef/poison, add it into canCreateUndefOrPoison return false 
FABS will not create undef/poison, add it into canCreateUndefOrPoison
return false
 [AMDGPU] Add freeze for LowerSELECT (#148796) 2025-07-18T05:29:33+00:00 Shoreshen 372660931@qq.com 2025-07-18T05:29:33+00:00 f761d73265119eeb3b1ab64543e6d3012078ad13 Trying to solve https://github.com/llvm/llvm-project/issues/147635 Add freeze for legalizer when breaking i64 select to 2 i32 select. Several tests changed, still need to investigate why. --------- Co-authored-by: Shilei Tian <i@tianshilei.me> 
Trying to solve https://github.com/llvm/llvm-project/issues/147635

Add freeze for legalizer when breaking i64 select to 2 i32 select.

Several tests changed, still need to investigate why.

---------

Co-authored-by: Shilei Tian <i@tianshilei.me>
 [AMDGPU][True16][CodeGen] sext i16 inreg in true16 mode (#144024) 2025-06-18T15:30:53+00:00 Brox Chen guochen2@amd.com 2025-06-18T15:30:53+00:00 9da9d32670ddbf610f0788236e78b2382037f00b update sext pattern in true16, setting up proper vgpr16 reg use 
update sext pattern in true16, setting up proper vgpr16 reg use
 [AMDGPU][True16][CodeGen] update GFX11Plus codegen test with true16 flag (#135078) 2025-04-23T17:06:52+00:00 Brox Chen guochen2@amd.com 2025-04-23T17:06:52+00:00 6dbc01e8015816e904687c03f0ea8afac817781d This is a NFC patch. This patch run a bulk update on CodeGen tests that are impacted by the true16 features. This patch applies: 1. duplicate GFX11plus runlines and apply them with "+mattr=+real-true16" and "+mattr=-real-true16" 2. update the test with the update script For some GISEL runlines, the current CodeGen do not fully support the true16 version. Still update the runlines, but comment out the failing one, and added a "FIXME-TRUE16" comment to that test for easier tracking. These test will be fixed in the following patches. This is in a transition state that we support both "+real-true16/-real-true16" in our code base. We plan to move to "+real-true16" as default, and finally remove "-real-true16" mode and test lines. 
This is a NFC patch.

This patch run a bulk update on CodeGen tests that are impacted by the
true16 features. This patch applies:
1. duplicate GFX11plus runlines and apply them with
"+mattr=+real-true16" and "+mattr=-real-true16"
2. update the test with the update script

For some GISEL runlines, the current CodeGen do not fully support the
true16 version. Still update the runlines, but comment out the failing
one, and added a "FIXME-TRUE16" comment to that test for easier
tracking. These test will be fixed in the following patches.

This is in a transition state that we support both
"+real-true16/-real-true16" in our code base. We plan to move to
"+real-true16" as default, and finally remove "-real-true16" mode and
test lines.
 [AMDGPU][True16][MC] true16 for v_frexp_mant_f16 (#120653) 2025-01-03T19:42:39+00:00 Brox Chen guochen2@amd.com 2025-01-03T19:42:39+00:00 3b72c62e7faa918d9a7e7439a4aa86d00921b0b8 Support true16 format for v_frexp_mant_f16 in MC 
Support true16 format for v_frexp_mant_f16 in MC
 [AMDGPU] Adding multiple use analysis to SIPeepholeSDWA (#94800) 2024-06-14T17:14:19+00:00 Brian Favela brianfavela@microsoft.com 2024-06-14T17:14:19+00:00 e7e90dd1c1014b4a7ef77f74af3682168d23ddbf Allow for multiple uses of an operand where each instruction can be promoted to SDWA. For instance: ; v_and_b32 v2, lit(0x0000ffff), v2 ; v_and_b32 v3, 6, v2 ; v_and_b32 v2, 1, v2 Can be folded to: ; v_and_b32 v3, 6, sel_lo(v2) ; v_and_b32 v2, 1, sel_lo(v2) 
Allow for multiple uses of an operand where each instruction can be
promoted to SDWA.

For instance:

; v_and_b32 v2, lit(0x0000ffff), v2
; v_and_b32 v3, 6, v2
; v_and_b32 v2, 1, v2

Can be folded to:
; v_and_b32 v3, 6, sel_lo(v2)
; v_and_b32 v2, 1, sel_lo(v2)
 [AMDGPU,test] Change llc -march= to -mtriple= (#75982) 2024-01-17T05:54:58+00:00 Fangrui Song i@maskray.me 2024-01-17T05:54:58+00:00 9e9907f1cfa424366fba58d9520f9305b537cec9 Similar to 806761a7629df268c8aed49657aeccffa6bca449. For IR files without a target triple, -mtriple= specifies the full target triple while -march= merely sets the architecture part of the default target triple, leaving a target triple which may not make sense, e.g. amdgpu-apple-darwin. Therefore, -march= is error-prone and not recommended for tests without a target triple. The issue has been benign as we recognize $unknown-apple-darwin as ELF instead of rejecting it outrightly. This patch changes AMDGPU tests to not rely on the default OS/environment components. Tests that need fixes are not changed: ``` LLVM :: CodeGen/AMDGPU/fabs.f64.ll LLVM :: CodeGen/AMDGPU/fabs.ll LLVM :: CodeGen/AMDGPU/floor.ll LLVM :: CodeGen/AMDGPU/fneg-fabs.f64.ll LLVM :: CodeGen/AMDGPU/fneg-fabs.ll LLVM :: CodeGen/AMDGPU/r600-infinite-loop-bug-while-reorganizing-vector.ll LLVM :: CodeGen/AMDGPU/schedule-if-2.ll ``` 
Similar to 806761a7629df268c8aed49657aeccffa6bca449.

For IR files without a target triple, -mtriple= specifies the full
target triple while -march= merely sets the architecture part of the
default target triple, leaving a target triple which may not make sense,
e.g. amdgpu-apple-darwin.

Therefore, -march= is error-prone and not recommended for tests without
a target triple. The issue has been benign as we recognize
$unknown-apple-darwin as ELF instead of rejecting it outrightly.

This patch changes AMDGPU tests to not rely on the default
OS/environment components. Tests that need fixes are not changed:

```
  LLVM :: CodeGen/AMDGPU/fabs.f64.ll
  LLVM :: CodeGen/AMDGPU/fabs.ll
  LLVM :: CodeGen/AMDGPU/floor.ll
  LLVM :: CodeGen/AMDGPU/fneg-fabs.f64.ll
  LLVM :: CodeGen/AMDGPU/fneg-fabs.ll
  LLVM :: CodeGen/AMDGPU/r600-infinite-loop-bug-while-reorganizing-vector.ll
  LLVM :: CodeGen/AMDGPU/schedule-if-2.ll
```
 [AMDGPU] Revert "Preliminary patch for divergence driven instruction selection. Operands Folding 1." (#71710) 2023-11-13T13:53:10+00:00 Jay Foad jay.foad@amd.com 2023-11-13T13:53:10+00:00 a4196666ac81fc098461559cf301fc7c78aa06f3 This reverts commit 201f892b3b597f24287ab6a712a286e25a45a7d9. 
This reverts commit 201f892b3b597f24287ab6a712a286e25a45a7d9.
 [AMDGPU] Select 64-bit imm moves if can be encoded as 32 bit operand (#70395) 2023-10-30T15:12:28+00:00 Stanislav Mekhanoshin rampitec@users.noreply.github.com 2023-10-30T15:12:28+00:00 fe8335babba1725e18d6ea94073c3dbb92958bfa This allows folding of 64-bit operands if fit into 32-bit. Fixes https://github.com/llvm/llvm-project/issues/67781 
This allows folding of 64-bit operands if fit into 32-bit. Fixes
https://github.com/llvm/llvm-project/issues/67781