llvm-project.git/llvm/test/CodeGen/AMDGPU/llvm.amdgcn.s.buffer.load.ll, branch users/nico/python-2

AMDGPU: Replace some float undef test uses with poison (#131090)

2025-03-13T13:07:48+00:00

[AMDGPU] Skip VGPR deallocation for waveslot limited kernels (#112765)

2024-10-21T16:39:52+00:00

MSG_DEALLOC_VGPRS slows down very small waveslot limited kernels. It's
been identified this message is only really needed for VGPR limited
kernels. A kernel becomes VGPR limited if a total number of VGPRs per
SIMD / number of used VGPRs is more than a number of wave slots.

[AMDGPU][SILoadStoreOptimizer] Include constrained buffer load variants (#101619)

2024-08-06T05:57:04+00:00

Use the constrained buffer load opcodes while combining under-aligned
loads for XNACK enabled subtargets.

[AMDGPU] CodeGen for GFX12 S_WAIT_* instructions (#77438)

2024-01-18T10:47:45+00:00

Update SIMemoryLegalizer and SIInsertWaitcnts to use separate wait
instructions per counter (e.g. S_WAIT_LOADCNT) and split VMCNT into
separate LOADCNT, SAMPLECNT and BVHCNT counters.

[AMDGPU] Work around s_getpc_b64 zero extending on GFX12 (#78186)

2024-01-18T10:23:27+00:00

[AMDGPU,test] Change llc -march= to -mtriple= (#75982)

2024-01-17T05:54:58+00:00

Similar to 806761a7629df268c8aed49657aeccffa6bca449.

For IR files without a target triple, -mtriple= specifies the full
target triple while -march= merely sets the architecture part of the
default target triple, leaving a target triple which may not make sense,
e.g. amdgpu-apple-darwin.

Therefore, -march= is error-prone and not recommended for tests without
a target triple. The issue has been benign as we recognize
$unknown-apple-darwin as ELF instead of rejecting it outrightly.

This patch changes AMDGPU tests to not rely on the default
OS/environment components. Tests that need fixes are not changed:

```
  LLVM :: CodeGen/AMDGPU/fabs.f64.ll
  LLVM :: CodeGen/AMDGPU/fabs.ll
  LLVM :: CodeGen/AMDGPU/floor.ll
  LLVM :: CodeGen/AMDGPU/fneg-fabs.f64.ll
  LLVM :: CodeGen/AMDGPU/fneg-fabs.ll
  LLVM :: CodeGen/AMDGPU/r600-infinite-loop-bug-while-reorganizing-vector.ll
  LLVM :: CodeGen/AMDGPU/schedule-if-2.ll
```

[AMDGPU] CodeGen for GFX12 VBUFFER instructions (#75492)

2023-12-15T12:45:03+00:00

[AMDGPU] CodeGen for SMEM instructions (#75579)

2023-12-15T11:10:33+00:00

[AMDGPU] Insert s_nop before s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)

2023-07-19T09:33:11+00:00

Differential Revision: https://reviews.llvm.org/D155681

[AMDGPU] Reimplement the GFX11 early release VGPRs optimization

2023-06-19T16:12:54+00:00

Implement this optimization in SIInsertWaitcnts, where we already have
information about whether there might be outstanding VMEM store
instructions. This has the following advantages:
- Correctly handles atomics-with-return.
- Correctly handles call instructions.
- Should be faster because it does not require running a separate pass.

Differential Revision: https://reviews.llvm.org/D153279