<feed xmlns='http://www.w3.org/2005/Atom'>
<title>llvm-project.git/llvm/test/CodeGen/AMDGPU/extract-subvector.ll, branch users/nico/python-2</title>
<subtitle>Unnamed repository; edit this file 'description' to name the repository.
</subtitle>
<link rel='alternate' type='text/html' href='https://git.belthelziquor.com/llvm-project.git/'/>
<entry>
<title>[AMDGPU][SIInsertWaitCnts] skip meta instructions early  (#145720)</title>
<updated>2025-07-01T16:32:48+00:00</updated>
<author>
<name>Sameer Sahasrabuddhe</name>
<email>sameer.sahasrabuddhe@amd.com</email>
</author>
<published>2025-07-01T16:32:48+00:00</published>
<link rel='alternate' type='text/html' href='https://git.belthelziquor.com/llvm-project.git/commit/?id=a34a02481246482a490c320afb7375ec24cb634e'/>
<id>a34a02481246482a490c320afb7375ec24cb634e</id>
<content type='text'>
When iterating over a block, meta instructions have no effect on wait counts,
but their presence drops the reference to earlier waitcnt instructions before
they are processed. This results in spurious wait counts, which do not affect
correctness, but are also not required in the resulting program. Skipping meta
instructions as soon as they are seen cleans this up.</content>
<content type='xhtml'>
<div xmlns='http://www.w3.org/1999/xhtml'>
<pre>
When iterating over a block, meta instructions have no effect on wait counts,
but their presence drops the reference to earlier waitcnt instructions before
they are processed. This results in spurious wait counts, which do not affect
correctness, but are also not required in the resulting program. Skipping meta
instructions as soon as they are seen cleans this up.</pre>
</div>
</content>
</entry>
<entry>
<title>[AMDGPU] Select (xor i1 (divergent trunc:i32 x), -1) -&gt; cmp_neq x, 1 (#133698)</title>
<updated>2025-04-11T11:03:01+00:00</updated>
<author>
<name>Ana Mihajlovic</name>
<email>Ana.Mihajlovic@amd.com</email>
</author>
<published>2025-04-11T11:03:01+00:00</published>
<link rel='alternate' type='text/html' href='https://git.belthelziquor.com/llvm-project.git/commit/?id=52a32471967f62ae4d1f905e7a2a5022be40a9c7'/>
<id>52a32471967f62ae4d1f905e7a2a5022be40a9c7</id>
<content type='text'>
</content>
<content type='xhtml'>
<div xmlns='http://www.w3.org/1999/xhtml'>
<pre>
</pre>
</div>
</content>
</entry>
<entry>
<title>AMDGPU: Replace tests using undef in shufflevector with poison (#130899)</title>
<updated>2025-03-12T13:45:02+00:00</updated>
<author>
<name>Matt Arsenault</name>
<email>Matthew.Arsenault@amd.com</email>
</author>
<published>2025-03-12T13:45:02+00:00</published>
<link rel='alternate' type='text/html' href='https://git.belthelziquor.com/llvm-project.git/commit/?id=b76e396990ef63fa6deb97ae88a6e1c076fc6717'/>
<id>b76e396990ef63fa6deb97ae88a6e1c076fc6717</id>
<content type='text'>
</content>
<content type='xhtml'>
<div xmlns='http://www.w3.org/1999/xhtml'>
<pre>
</pre>
</div>
</content>
</entry>
<entry>
<title>[AMDGPU] Filter candidates of LiveRegOptimizer for profitable cases (#124624)</title>
<updated>2025-03-05T23:44:48+00:00</updated>
<author>
<name>choikwa</name>
<email>5455710+choikwa@users.noreply.github.com</email>
</author>
<published>2025-03-05T23:44:48+00:00</published>
<link rel='alternate' type='text/html' href='https://git.belthelziquor.com/llvm-project.git/commit/?id=45759fe5b49148aa724d9d58d03e507938c7d218'/>
<id>45759fe5b49148aa724d9d58d03e507938c7d218</id>
<content type='text'>
It is known that for vector whose element fits in i16 will be split and
scalarized in SelectionDag's type legalizer
(see SIISelLowering::getPreferredVectorAction).

LRO attempts to undo the scalarizing of vectors across basic block
boundary and shoehorn Values in VGPRs. LRO is beneficial for operations
that natively work on illegal vector types to prevent flip-flopping
between unpacked and packed. If we know that operations on vector will
be split and scalarized, then we don't want to shoehorn them back to
packed VGPR.

Operations that we know to work natively on illegal vector types usually
come in the form of intrinsics (MFMA, DOT8), buffer store, shuffle, phi
nodes to name a few.</content>
<content type='xhtml'>
<div xmlns='http://www.w3.org/1999/xhtml'>
<pre>
It is known that for vector whose element fits in i16 will be split and
scalarized in SelectionDag's type legalizer
(see SIISelLowering::getPreferredVectorAction).

LRO attempts to undo the scalarizing of vectors across basic block
boundary and shoehorn Values in VGPRs. LRO is beneficial for operations
that natively work on illegal vector types to prevent flip-flopping
between unpacked and packed. If we know that operations on vector will
be split and scalarized, then we don't want to shoehorn them back to
packed VGPR.

Operations that we know to work natively on illegal vector types usually
come in the form of intrinsics (MFMA, DOT8), buffer store, shuffle, phi
nodes to name a few.</pre>
</div>
</content>
</entry>
<entry>
<title>[AMDGPU] Reland: Add IR LiveReg type-based optimization</title>
<updated>2024-07-03T16:26:19+00:00</updated>
<author>
<name>Jeffrey Byrnes</name>
<email>Jeffrey.Byrnes@amd.com</email>
</author>
<published>2023-09-14T19:20:06+00:00</published>
<link rel='alternate' type='text/html' href='https://git.belthelziquor.com/llvm-project.git/commit/?id=5da7179cb3ff80203f58ddea71562816b2ae4ff6'/>
<id>5da7179cb3ff80203f58ddea71562816b2ae4ff6</id>
<content type='text'>
</content>
<content type='xhtml'>
<div xmlns='http://www.w3.org/1999/xhtml'>
<pre>
</pre>
</div>
</content>
</entry>
<entry>
<title>Revert "[AMDGPU] Add IR LiveReg type-based optimization" (#97138)</title>
<updated>2024-06-29T06:18:26+00:00</updated>
<author>
<name>Vitaly Buka</name>
<email>vitalybuka@google.com</email>
</author>
<published>2024-06-29T06:18:26+00:00</published>
<link rel='alternate' type='text/html' href='https://git.belthelziquor.com/llvm-project.git/commit/?id=3e53c97d33210db68188e731e93ee48dbaeeae32'/>
<id>3e53c97d33210db68188e731e93ee48dbaeeae32</id>
<content type='text'>
Part of #66838.

https://lab.llvm.org/buildbot/#/builders/52/builds/404
https://lab.llvm.org/buildbot/#/builders/55/builds/358
https://lab.llvm.org/buildbot/#/builders/164/builds/518

This reverts commit ded956440739ae326a99cbaef18ce4362e972679.</content>
<content type='xhtml'>
<div xmlns='http://www.w3.org/1999/xhtml'>
<pre>
Part of #66838.

https://lab.llvm.org/buildbot/#/builders/52/builds/404
https://lab.llvm.org/buildbot/#/builders/55/builds/358
https://lab.llvm.org/buildbot/#/builders/164/builds/518

This reverts commit ded956440739ae326a99cbaef18ce4362e972679.</pre>
</div>
</content>
</entry>
<entry>
<title>[AMDGPU] Add IR LiveReg type-based optimization</title>
<updated>2024-06-28T22:01:39+00:00</updated>
<author>
<name>Jeffrey Byrnes</name>
<email>Jeffrey.Byrnes@amd.com</email>
</author>
<published>2023-09-14T19:20:06+00:00</published>
<link rel='alternate' type='text/html' href='https://git.belthelziquor.com/llvm-project.git/commit/?id=ded956440739ae326a99cbaef18ce4362e972679'/>
<id>ded956440739ae326a99cbaef18ce4362e972679</id>
<content type='text'>
Change-Id: Ia0d11b79b8302e79247fe193ccabc0dad2d359a0
</content>
<content type='xhtml'>
<div xmlns='http://www.w3.org/1999/xhtml'>
<pre>
Change-Id: Ia0d11b79b8302e79247fe193ccabc0dad2d359a0
</pre>
</div>
</content>
</entry>
<entry>
<title>[AMDGPU] Remove repeated -mtriple options from RUN lines (#66486)</title>
<updated>2023-09-15T10:29:24+00:00</updated>
<author>
<name>Jay Foad</name>
<email>jay.foad@amd.com</email>
</author>
<published>2023-09-15T10:29:24+00:00</published>
<link rel='alternate' type='text/html' href='https://git.belthelziquor.com/llvm-project.git/commit/?id=ceb68eea8c5cfd7893d55afaef93932762bbebaa'/>
<id>ceb68eea8c5cfd7893d55afaef93932762bbebaa</id>
<content type='text'>
</content>
<content type='xhtml'>
<div xmlns='http://www.w3.org/1999/xhtml'>
<pre>
</pre>
</div>
</content>
</entry>
<entry>
<title>[test] Change llc -march= to -mtriple=</title>
<updated>2023-09-11T21:42:37+00:00</updated>
<author>
<name>Fangrui Song</name>
<email>i@maskray.me</email>
</author>
<published>2023-09-11T21:42:37+00:00</published>
<link rel='alternate' type='text/html' href='https://git.belthelziquor.com/llvm-project.git/commit/?id=806761a7629df268c8aed49657aeccffa6bca449'/>
<id>806761a7629df268c8aed49657aeccffa6bca449</id>
<content type='text'>
The issue is uncovered by #47698: for IR files without a target triple,
-mtriple= specifies the full target triple while -march= merely sets the
architecture part of the default target triple, leaving a target triple which
may not make sense, e.g. riscv64-apple-darwin.

Therefore, -march= is error-prone and not recommended for tests without a target
triple. The issue has been benign as we recognize $unknown-apple-darwin as ELF instead
of rejecting it outrightly.
</content>
<content type='xhtml'>
<div xmlns='http://www.w3.org/1999/xhtml'>
<pre>
The issue is uncovered by #47698: for IR files without a target triple,
-mtriple= specifies the full target triple while -march= merely sets the
architecture part of the default target triple, leaving a target triple which
may not make sense, e.g. riscv64-apple-darwin.

Therefore, -march= is error-prone and not recommended for tests without a target
triple. The issue has been benign as we recognize $unknown-apple-darwin as ELF instead
of rejecting it outrightly.
</pre>
</div>
</content>
</entry>
<entry>
<title>[test] Remove occurences of br undef in CodeGen/AMDGPU tests</title>
<updated>2023-04-18T07:47:29+00:00</updated>
<author>
<name>Kriti Gupta</name>
<email>kriti.gupta@research.iiit.ac.in</email>
</author>
<published>2023-04-18T07:46:54+00:00</published>
<link rel='alternate' type='text/html' href='https://git.belthelziquor.com/llvm-project.git/commit/?id=a3dfa4e08350b037659f9fa09eddedfe4b471296'/>
<id>a3dfa4e08350b037659f9fa09eddedfe4b471296</id>
<content type='text'>
Differential Revision: https://reviews.llvm.org/D148041
</content>
<content type='xhtml'>
<div xmlns='http://www.w3.org/1999/xhtml'>
<pre>
Differential Revision: https://reviews.llvm.org/D148041
</pre>
</div>
</content>
</entry>
</feed>
