llvm-project.git/llvm/test/CodeGen/AMDGPU/ds-sub-offset.ll, branch users/nico/python-2 Unnamed repository; edit this file 'description' to name the repository. AMDGPU: Mark workitem ID intrinsics with range attribute (#136196) 2025-04-18T10:27:38+00:00 Matt Arsenault Matthew.Arsenault@amd.com 2025-04-18T10:27:38+00:00 9bdd9dc895ade41ec24f1a9918f70b23271ac89b This avoids the need to have special handling at every use site. Unfortunately this means we unnecessarily emit AssertZext in the DAG (where we already directly understand the range of the intrinsic), andt we regress in undefined cases as we don't fold out asserts on undef. 
This avoids the need to have special handling at every use site.
Unfortunately this means we unnecessarily emit AssertZext in the DAG
(where we already directly understand the range of the intrinsic), andt
we regress in undefined cases as we don't fold out asserts on undef.
 [AMDGPU][True16][CodeGen] D16 LDS load/store pseudo instructions in true16 (#131427) 2025-03-17T14:28:45+00:00 Brox Chen guochen2@amd.com 2025-03-17T14:28:45+00:00 8bc0f879a05228c58235ded510360da2220f0afd Implement new pseudos with the suffix _t16 which have VGPR_16 as the store src or load dst. This affects LDS 8 and 16-bit loads and stores. Lower the pseudos to the existing real Hi/Lo instructions in MC inst layer with VGPR_32 src or dst --------- Co-authored-by: Abhinav <abhinav.garg@amd.com> 
Implement new pseudos with the suffix _t16 which have VGPR_16 as the
store src or load dst. This affects LDS 8 and 16-bit loads and stores.
Lower the pseudos to the existing real Hi/Lo instructions in MC inst
layer with VGPR_32 src or dst

---------

Co-authored-by: Abhinav <abhinav.garg@amd.com>
 AMDGPU: Replace undef global initializers in tests with poison (#131051) 2025-03-13T06:41:03+00:00 Matt Arsenault Matthew.Arsenault@amd.com 2025-03-13T06:41:03+00:00 26ae98c4d73d13f973eeb8450e0f5c7d1cd25993 






PeepholeOpt: Allow introducing subregister uses on reg_sequence (#127052)
2025-02-22T02:16:14+00:00

Matt Arsenault
Matthew.Arsenault@amd.com

2025-02-22T02:16:14+00:00

1bb43068f187141f20066a83675531161ed45051

This reverts d246cc618adc52fdbd69d44a2a375c8af97b6106. We now handle
composing subregister extracts through reg_sequence.




This reverts d246cc618adc52fdbd69d44a2a375c8af97b6106. We now handle
composing subregister extracts through reg_sequence.






Reapply "[AMDGPU] Still set up the two SGPRs for queue ptr even it is COV5 (#112403)"
2024-11-09T01:21:16+00:00

Shilei Tian
i@tianshilei.me

2024-11-09T01:21:16+00:00

6548b6354d1d990e1c98736f5e7c3de876bedc8e

This reverts commit ca33649abe5fad93c57afef54e43ed9b3249cd86.





This reverts commit ca33649abe5fad93c57afef54e43ed9b3249cd86.







Revert "[AMDGPU] Still set up the two SGPRs for queue ptr even it is COV5 (#112403)"
2024-11-08T21:36:35+00:00

Shilei Tian
i@tianshilei.me

2024-11-08T21:36:10+00:00

ca33649abe5fad93c57afef54e43ed9b3249cd86

This reverts commit e215a1e27d84adad2635a52393621eb4fa439dc9 as it broke both
hip and openmp buildbots.





This reverts commit e215a1e27d84adad2635a52393621eb4fa439dc9 as it broke both
hip and openmp buildbots.







[AMDGPU] Still set up the two SGPRs for queue ptr even it is COV5 (#112403)
2024-11-08T18:05:35+00:00

Shilei Tian
i@tianshilei.me

2024-11-08T18:05:35+00:00

e215a1e27d84adad2635a52393621eb4fa439dc9












[AMDGPU] Skip VGPR deallocation for waveslot limited kernels (#112765)
2024-10-21T16:39:52+00:00

Stanislav Mekhanoshin
rampitec@users.noreply.github.com

2024-10-21T16:39:52+00:00

3277c7cd28154e33637a168acb26cea7ac1f7fff

MSG_DEALLOC_VGPRS slows down very small waveslot limited kernels. It's
been identified this message is only really needed for VGPR limited
kernels. A kernel becomes VGPR limited if a total number of VGPRs per
SIMD / number of used VGPRs is more than a number of wave slots.




MSG_DEALLOC_VGPRS slows down very small waveslot limited kernels. It's
been identified this message is only really needed for VGPR limited
kernels. A kernel becomes VGPR limited if a total number of VGPRs per
SIMD / number of used VGPRs is more than a number of wave slots.






Reapply "AMDGPU: Move attributor into optimization pipeline (#83131)" and follow up commit "clang/AMDGPU: Defeat attribute optimization in attribute test" (#98851)
2024-07-15T07:51:44+00:00

Matt Arsenault
Matthew.Arsenault@amd.com

2024-07-15T05:59:07+00:00

b1bcb7ca460fcd317bbc8309e14c8761bf8394e0

This reverts commit adaff46d087799072438dd744b038e6fd50a2d78.

Drop the -O3 checks from default-attributes.hip. I don't know why they
are different on some bots but reverting this is far too disruptive.





This reverts commit adaff46d087799072438dd744b038e6fd50a2d78.

Drop the -O3 checks from default-attributes.hip. I don't know why they
are different on some bots but reverting this is far too disruptive.







Revert "AMDGPU: Move attributor into optimization pipeline (#83131)" and follow up commit "clang/AMDGPU: Defeat attribute optimization in attribute test" (#98851)
2024-07-15T01:48:54+00:00

dyung
douglas.yung@sony.com

2024-07-15T01:48:54+00:00

adaff46d087799072438dd744b038e6fd50a2d78

This reverts commits 677cc15e0ff2e0e6aa30538eb187990a6a8f53c0 and
78bc1b64a6dc3fb6191355a5e1b502be8b3668e7.

The test CodeGenHIP/default-attributes.hip is failing on multiple bots
even after the attempted fix including the following:
- https://lab.llvm.org/buildbot/#/builders/3/builds/1473
- https://lab.llvm.org/buildbot/#/builders/65/builds/1380
- https://lab.llvm.org/buildbot/#/builders/161/builds/595
- https://lab.llvm.org/buildbot/#/builders/154/builds/1372
- https://lab.llvm.org/buildbot/#/builders/133/builds/1547
- https://lab.llvm.org/buildbot/#/builders/81/builds/755
- https://lab.llvm.org/buildbot/#/builders/40/builds/570
- https://lab.llvm.org/buildbot/#/builders/13/builds/748
- https://lab.llvm.org/buildbot/#/builders/12/builds/1845
- https://lab.llvm.org/buildbot/#/builders/11/builds/1695
- https://lab.llvm.org/buildbot/#/builders/190/builds/1829
- https://lab.llvm.org/buildbot/#/builders/193/builds/962
- https://lab.llvm.org/buildbot/#/builders/23/builds/991
- https://lab.llvm.org/buildbot/#/builders/144/builds/2256
- https://lab.llvm.org/buildbot/#/builders/46/builds/1614

These bots have been broken for a day, so reverting to get everything
back to green.




This reverts commits 677cc15e0ff2e0e6aa30538eb187990a6a8f53c0 and
78bc1b64a6dc3fb6191355a5e1b502be8b3668e7.

The test CodeGenHIP/default-attributes.hip is failing on multiple bots
even after the attempted fix including the following:
- https://lab.llvm.org/buildbot/#/builders/3/builds/1473
- https://lab.llvm.org/buildbot/#/builders/65/builds/1380
- https://lab.llvm.org/buildbot/#/builders/161/builds/595
- https://lab.llvm.org/buildbot/#/builders/154/builds/1372
- https://lab.llvm.org/buildbot/#/builders/133/builds/1547
- https://lab.llvm.org/buildbot/#/builders/81/builds/755
- https://lab.llvm.org/buildbot/#/builders/40/builds/570
- https://lab.llvm.org/buildbot/#/builders/13/builds/748
- https://lab.llvm.org/buildbot/#/builders/12/builds/1845
- https://lab.llvm.org/buildbot/#/builders/11/builds/1695
- https://lab.llvm.org/buildbot/#/builders/190/builds/1829
- https://lab.llvm.org/buildbot/#/builders/193/builds/962
- https://lab.llvm.org/buildbot/#/builders/23/builds/991
- https://lab.llvm.org/buildbot/#/builders/144/builds/2256
- https://lab.llvm.org/buildbot/#/builders/46/builds/1614

These bots have been broken for a day, so reverting to get everything
back to green.