llvm-project.git/llvm/test/CodeGen/AMDGPU/atomic_optimizations_pixelshader.ll, branch users/nico/python-2 Unnamed repository; edit this file 'description' to name the repository. Reland "[AMDGPU] Remove s_delay_alu for VALU->SGPR->SALU (#127212)" (#131111) 2025-03-13T09:26:20+00:00 Ana Mihajlovic Ana.Mihajlovic@amd.com 2025-03-13T09:26:20+00:00 459b4e3fe10805b110bc89aa857532715bfe54e0 We have a VALU->SGPR->SALU (VALU writing to SGPR and SALU reading from it). When VALU is issued, it increments internal counter VA_SDST used to track use of this SGPR. SALU will not issue until VA_SDST is zero, that is when VALU is finished writing. Therefore, delays added by s_delay_alu are not needed in this situation. 
We have a VALU->SGPR->SALU (VALU writing to SGPR and SALU reading from
it). When VALU is issued, it increments internal counter VA_SDST used to
track use of this SGPR. SALU will not issue until VA_SDST is zero, that
is when VALU is finished writing. Therefore, delays added by s_delay_alu
are not needed in this situation.
 Revert "[AMDGPU] Remove s_delay_alu for VALU->SGPR->SALU (#127212)" 2025-03-12T19:09:09+00:00 Kazu Hirata kazu@google.com 2025-03-12T19:09:09+00:00 aa008e00085a260b2ed130b3430cc4640144ab30 This reverts commit 71582c6667a6334c688734cae628e906b3c1ac1d. Multiple buildbot failures have been reported: https://github.com/llvm/llvm-project/pull/127212 
This reverts commit 71582c6667a6334c688734cae628e906b3c1ac1d.

Multiple buildbot failures have been reported:
https://github.com/llvm/llvm-project/pull/127212
[AMDGPU] Remove s_delay_alu for VALU->SGPR->SALU (#127212) 2025-03-12T16:33:07+00:00 Ana Mihajlovic Ana.Mihajlovic@amd.com 2025-03-12T16:33:07+00:00 71582c6667a6334c688734cae628e906b3c1ac1d We have a VALU->SGPR->SALU (VALU writing to SGPR and SALU reading from it). When VALU is issued, it increments internal counter VA_SDST used to track use of this SGPR. SALU will not issue until VA_SDST is zero, that is when VALU is finished writing. Therefore, delays added by s_delay_alu are not needed in this situation. 
We have a VALU->SGPR->SALU (VALU writing to SGPR and SALU reading from
it). When VALU is issued, it increments internal counter VA_SDST used to
track use of this SGPR. SALU will not issue until VA_SDST is zero, that
is when VALU is finished writing. Therefore, delays added by s_delay_alu
are not needed in this situation.
 [AMDGPU] Skip VGPR deallocation for waveslot limited kernels (#112765) 2024-10-21T16:39:52+00:00 Stanislav Mekhanoshin rampitec@users.noreply.github.com 2024-10-21T16:39:52+00:00 3277c7cd28154e33637a168acb26cea7ac1f7fff MSG_DEALLOC_VGPRS slows down very small waveslot limited kernels. It's been identified this message is only really needed for VGPR limited kernels. A kernel becomes VGPR limited if a total number of VGPRs per SIMD / number of used VGPRs is more than a number of wave slots. 
MSG_DEALLOC_VGPRS slows down very small waveslot limited kernels. It's
been identified this message is only really needed for VGPR limited
kernels. A kernel becomes VGPR limited if a total number of VGPRs per
SIMD / number of used VGPRs is more than a number of wave slots.
 [AMDGPU] V_SET_INACTIVE optimizations (#98864) 2024-09-05T05:39:28+00:00 Carl Ritson carl.ritson@amd.com 2024-09-05T05:39:28+00:00 16cda01d22c0ac1713f667d501bdca91594a4e13 Optimize V_SET_INACTIVE by allow it to run in WWM. Hence WWM sections are not broken up for inactive lane setting. WWM V_SET_INACTIVE can typically be lower to V_CNDMASK. Some cases require use of exec manipulation V_MOV as previous code. GFX9 sees slight instruction count increase in edge cases due to smaller constant bus. Additionally avoid introducing exec manipulation and V_MOVs where a source of V_SET_INACTIVE is the destination. This is a common pattern as WWM register pre-allocation often assigns the same register. 
Optimize V_SET_INACTIVE by allow it to run in WWM.
Hence WWM sections are not broken up for inactive lane setting.
WWM V_SET_INACTIVE can typically be lower to V_CNDMASK.
Some cases require use of exec manipulation V_MOV as previous code.
GFX9 sees slight instruction count increase in edge cases due to
smaller constant bus.

Additionally avoid introducing exec manipulation and V_MOVs where
a source of V_SET_INACTIVE is the destination.
This is a common pattern as WWM register pre-allocation often
assigns the same register.
 [AMDGPU] Improve codegen for GFX10+ DPP reductions and scans (#107108) 2024-09-04T10:03:22+00:00 Jay Foad jay.foad@amd.com 2024-09-04T10:03:22+00:00 126d6f27102fca0d69dc50cf29a37442d18304cf Use poison for an unused input to the permlanex16 intrinsic, to improve register allocation and avoid an unnecessary v_mov instruction. 
Use poison for an unused input to the permlanex16 intrinsic, to improve
register allocation and avoid an unnecessary v_mov instruction.
 [AMDGPU] Remove -wavefrontsize32 and -wavefrontsize64 from GFX10+ tests (NFC) (#100711) 2024-07-26T07:42:24+00:00 Changpeng Fang changpeng.fang@amd.com 2024-07-26T07:42:24+00:00 a82032918cd445e5750e171f57d4f3d7096c021a They are no longer needed after the patch: [AMDGPU] Remove wavefrontsize feature from GFX10: https://github.com/llvm/llvm-project/pull/98400 The exception is when "target-features" are set to "+wavefrontsize32" or "+wavefrontsize64", we still need to remove a wavefrontsize feature before add a different one to make sure only one of them are present. 
They are no longer needed after the patch: [AMDGPU] Remove wavefrontsize
feature from GFX10: https://github.com/llvm/llvm-project/pull/98400
The exception is when "target-features" are set to "+wavefrontsize32" or
"+wavefrontsize64", we still need to remove a wavefrontsize feature
before add a different one to make sure only one of them are present.
 [MCP] Remove dead copies from basic blocks with successors. (#86973) 2024-03-28T21:43:49+00:00 Craig Topper craig.topper@sifive.com 2024-03-28T21:43:49+00:00 23d45e55edb0ca4567f5876e7051ff4a649213df Previously we wouldn't remove dead copies from basic blocks with successors. The comment said we didn't want to trust the live-in lists. The comment is very old so I'm not sure if that's still a concern today. This patch checks the live-in lists and removes copies from MaybeDeadCopies if they are referenced by any live-ins in any successors. We only do this if the tracksLiveness property is set. If that property is not set, we retain the old behavior. 
Previously we wouldn't remove dead copies from basic blocks with
successors. The comment said we didn't want to trust the live-in lists.
The comment is very old so I'm not sure if that's still a concern today.

This patch checks the live-in lists and removes copies from
MaybeDeadCopies if they are referenced by any live-ins in any
successors. We only do this if the tracksLiveness property is set. If
that property is not set, we retain the old behavior.
 [AMDGPU] Reorder atomic optimizer to avoid CAS loop. 2023-08-30T16:05:21+00:00 Pravin Jagtap Pravin.Jagtap@amd.com 2023-08-30T16:05:20+00:00 6ef6c954c6dcd34b99897cc00da9bf1b651398b5 Expand-Atomic pass emits the CAS loop for FP operations which limits the optimizations offered by atomic optimizer. Moving atomic optimizer before expand-atomics allows better codegen. Reviewed By: arsenm, #amdgpu Differential Revision: https://reviews.llvm.org/D157265 
Expand-Atomic pass emits the CAS loop for FP operations
which limits the optimizations offered by atomic optimizer.

Moving atomic optimizer before expand-atomics allows
better codegen.

Reviewed By: arsenm, #amdgpu

Differential Revision: https://reviews.llvm.org/D157265
[AMDGPU] Insert s_nop before s_sendmsg sendmsg(MSG_DEALLOC_VGPRS) 2023-07-19T09:33:11+00:00 Jay Foad jay.foad@amd.com 2023-07-19T07:29:14+00:00 7fa7a08f2104c026ff05cfaf536c60ad166cc6f8 Differential Revision: https://reviews.llvm.org/D155681 
Differential Revision: https://reviews.llvm.org/D155681