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<title>llvm-project.git/llvm/test/CodeGen/AMDGPU/amdgpu-simplify-libcall-rootn.ll, branch users/nico/python-2</title>
<subtitle>Unnamed repository; edit this file 'description' to name the repository.
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<entry>
<title>[AMDGPU] Remove explicit datalayout from tests where not needed</title>
<updated>2025-04-30T17:58:17+00:00</updated>
<author>
<name>Alexander Richardson</name>
<email>alexrichardson@google.com</email>
</author>
<published>2025-04-30T17:58:17+00:00</published>
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Since e39f6c1844fab59c638d8059a6cf139adb42279a opt will infer the
correct datalayout when given a triple. Avoid explicitly specifying it
in tests that depend on the AMDGPU target being present to avoid the
string becoming out of sync with the TargetInfo value.
Only tests with REQUIRES: amdgpu-registered-target or a local lit.cfg
were updated to ensure that tests for non-target-specific passes that
happen to use the AMDGPU layout still pass when building with a limited
set of targets.

Reviewed By: shiltian, arsenm

Pull Request: https://github.com/llvm/llvm-project/pull/137921
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Since e39f6c1844fab59c638d8059a6cf139adb42279a opt will infer the
correct datalayout when given a triple. Avoid explicitly specifying it
in tests that depend on the AMDGPU target being present to avoid the
string becoming out of sync with the TargetInfo value.
Only tests with REQUIRES: amdgpu-registered-target or a local lit.cfg
were updated to ensure that tests for non-target-specific passes that
happen to use the AMDGPU layout still pass when building with a limited
set of targets.

Reviewed By: shiltian, arsenm

Pull Request: https://github.com/llvm/llvm-project/pull/137921
</pre>
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</entry>
<entry>
<title>[LLVM][IR] Use splat syntax when printing Constant[Data]Vector. (#112548)</title>
<updated>2024-11-06T11:53:33+00:00</updated>
<author>
<name>Paul Walker</name>
<email>paul.walker@arm.com</email>
</author>
<published>2024-11-06T11:53:33+00:00</published>
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</entry>
<entry>
<title>AMDGPU: Emit 1/llvm.sqrt(x) instead of rsqrt calls in libcall handling (#92863)</title>
<updated>2024-05-21T16:42:45+00:00</updated>
<author>
<name>Matt Arsenault</name>
<email>Matthew.Arsenault@amd.com</email>
</author>
<published>2024-05-21T16:42:45+00:00</published>
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<id>dab1f7c8d3d7bf5021cdb96af74d533753ad2e23</id>
<content type='text'>
With the contract flag we should end up codegening to the rsqrt
instruction, or denormal corrected rsqrt sequence present in the
library.</content>
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<pre>
With the contract flag we should end up codegening to the rsqrt
instruction, or denormal corrected rsqrt sequence present in the
library.</pre>
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</content>
</entry>
<entry>
<title>AMDGPU: Directly emit sqrt intrinsic when folding rootn(x, 2) (#92598)</title>
<updated>2024-05-21T05:57:04+00:00</updated>
<author>
<name>Matt Arsenault</name>
<email>Matthew.Arsenault@amd.com</email>
</author>
<published>2024-05-21T05:57:04+00:00</published>
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<id>66b76faffb211b3cb2d58e3ab9401e6396447de9</id>
<content type='text'>
This avoids depending on pre/post link runs.

Depends #92595</content>
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This avoids depending on pre/post link runs.

Depends #92595</pre>
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</entry>
<entry>
<title>AMDGPU: Don't fold rootn(x, 1) to input for strictfp functions (#92595)</title>
<updated>2024-05-20T20:23:02+00:00</updated>
<author>
<name>Matt Arsenault</name>
<email>Matthew.Arsenault@amd.com</email>
</author>
<published>2024-05-20T20:23:02+00:00</published>
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<id>3cb1fe60fb00ba3761e34866ffc93c7d7a0b509d</id>
<content type='text'>
We need to insert a constrained canonicalize.

Depends #92594</content>
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We need to insert a constrained canonicalize.

Depends #92594</pre>
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</entry>
<entry>
<title>AMDGPU: Relax vector restriction for rootn libcall folds (#92594)</title>
<updated>2024-05-20T16:36:17+00:00</updated>
<author>
<name>Matt Arsenault</name>
<email>Matthew.Arsenault@amd.com</email>
</author>
<published>2024-05-20T16:36:17+00:00</published>
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<content type='text'>
We could try harder for nonsplat vectors but probably not worth the
effort.</content>
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<pre>
We could try harder for nonsplat vectors but probably not worth the
effort.</pre>
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</entry>
<entry>
<title>[FPEnv][AMDGPU] Correct AMDGPUSimplifyLibCalls handling of strictfp attribute. (#86705)</title>
<updated>2024-03-27T14:20:00+00:00</updated>
<author>
<name>Kevin P. Neal</name>
<email>52762977+kpneal@users.noreply.github.com</email>
</author>
<published>2024-03-27T14:20:00+00:00</published>
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<content type='text'>
The AMDGPUSimplifyLibCalls pass was lowering function calls with the
strictfp attribute to sequences that included function calls incorrectly
lacking the attribute. This patch corrects that.

The pass now also emits the correct constrained fp call instead of
normal FP instructions when in a function with the strictfp attribute.
Replacing non-constrained calls with constrained calls when required
is still on the IRBuilder's TODO list.</content>
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<pre>
The AMDGPUSimplifyLibCalls pass was lowering function calls with the
strictfp attribute to sequences that included function calls incorrectly
lacking the attribute. This patch corrects that.

The pass now also emits the correct constrained fp call instead of
normal FP instructions when in a function with the strictfp attribute.
Replacing non-constrained calls with constrained calls when required
is still on the IRBuilder's TODO list.</pre>
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</content>
</entry>
<entry>
<title>[AMDGPU] - Add address space for strided buffers (#74471)</title>
<updated>2023-12-15T14:49:25+00:00</updated>
<author>
<name>Jessica Del</name>
<email>50999226+OutOfCache@users.noreply.github.com</email>
</author>
<published>2023-12-15T14:49:25+00:00</published>
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<content type='text'>
This is an experimental address space for strided buffers. These buffers
can have structs as elements and
a stride &gt; 1.
These pointers allow the indexed access in units of stride, i.e., they
point at `buffer[index * stride]`.
Thus, we can use the `idxen` modifier for buffer loads.

We assign address space 9 to 192-bit buffer pointers which contain a
128-bit descriptor, a 32-bit offset and a 32-bit index. Essentially,
they are fat buffer pointers with an additional 32-bit index.</content>
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<pre>
This is an experimental address space for strided buffers. These buffers
can have structs as elements and
a stride &gt; 1.
These pointers allow the indexed access in units of stride, i.e., they
point at `buffer[index * stride]`.
Thus, we can use the `idxen` modifier for buffer loads.

We assign address space 9 to 192-bit buffer pointers which contain a
128-bit descriptor, a 32-bit offset and a 32-bit index. Essentially,
they are fat buffer pointers with an additional 32-bit index.</pre>
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</content>
</entry>
<entry>
<title>AMDGPU: Add more tests for rootn libcall handling</title>
<updated>2023-12-02T14:53:31+00:00</updated>
<author>
<name>Matt Arsenault</name>
<email>Matthew.Arsenault@amd.com</email>
</author>
<published>2023-12-02T03:38:21+00:00</published>
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