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<title>llvm-project.git/llvm/test/CodeGen/AMDGPU/amdgpu-codegenprepare-idiv.ll, branch users/nico/python-2</title>
<subtitle>Unnamed repository; edit this file 'description' to name the repository.
</subtitle>
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<entry>
<title>[AMDGPU] Handle CreateBinOp not returning BinaryOperator (#137791)</title>
<updated>2025-05-29T17:10:35+00:00</updated>
<author>
<name>anjenner</name>
<email>161845516+anjenner@users.noreply.github.com</email>
</author>
<published>2025-05-29T17:10:35+00:00</published>
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<id>a36cb01ea7750373739c206f86abcce0dbf9df5f</id>
<content type='text'>
AMDGPUCodeGenPrepareImpl::visitBinaryOperator() calls
Builder.CreateBinOp() and casts the resulting Value as a BinaryOperator
without checking, leading to an assert failure in a case found by
fuzzing. In this case, the operands are constant and CreateBinOp does
constant folding so returns a Constant instead of a BinaryOperator.</content>
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<pre>
AMDGPUCodeGenPrepareImpl::visitBinaryOperator() calls
Builder.CreateBinOp() and casts the resulting Value as a BinaryOperator
without checking, leading to an assert failure in a case found by
fuzzing. In this case, the operands are constant and CreateBinOp does
constant folding so returns a Constant instead of a BinaryOperator.</pre>
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</content>
</entry>
<entry>
<title>Reapply [AMDGPU] SIFixSgprCopies should not process twice VGPR to SGPR copies inserted by PHI preprocessing. (#135243)</title>
<updated>2025-04-10T20:18:21+00:00</updated>
<author>
<name>alex-t</name>
<email>alex-t@users.noreply.github.com</email>
</author>
<published>2025-04-10T20:18:21+00:00</published>
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<id>edd7b559c09e8e9b1fd0fc1905f0aaa67c74331f</id>
<content type='text'>
LIT tests which were incorrectly merged are corrected.</content>
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<pre>
LIT tests which were incorrectly merged are corrected.</pre>
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</entry>
<entry>
<title>Revert "[AMDGPU] SIFixSgprCopies should not process twice VGPR to SGPR copies inserted by PHI preprocessing. (#134153)"</title>
<updated>2025-04-10T17:20:01+00:00</updated>
<author>
<name>Nico Weber</name>
<email>thakis@chromium.org</email>
</author>
<published>2025-04-10T17:20:01+00:00</published>
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<id>464035fc7de52b6fe9b09c9f4c9a19fd5d46fcae</id>
<content type='text'>
This reverts commit 0563569978fee1e780a560494c89869074933f58.

Breaks tests, see comments on https://github.com/llvm/llvm-project/pull/134153
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<pre>
This reverts commit 0563569978fee1e780a560494c89869074933f58.

Breaks tests, see comments on https://github.com/llvm/llvm-project/pull/134153
</pre>
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</content>
</entry>
<entry>
<title>[AMDGPU] SIFixSgprCopies should not process twice VGPR to SGPR copies inserted by PHI preprocessing. (#134153)</title>
<updated>2025-04-10T16:30:52+00:00</updated>
<author>
<name>alex-t</name>
<email>alex-t@users.noreply.github.com</email>
</author>
<published>2025-04-10T16:30:52+00:00</published>
<link rel='alternate' type='text/html' href='https://git.belthelziquor.com/llvm-project.git/commit/?id=0563569978fee1e780a560494c89869074933f58'/>
<id>0563569978fee1e780a560494c89869074933f58</id>
<content type='text'>
PHI operands and results must belong to the same register class.
If a PHI node produces an SGPR, but one of its operands is a VGPR, we
insert a VGPR-to-SGPR copy in the operand’s source block. The PHI
operand is then updated to use the destination register of the inserted
copy.

These inserted copies are processed immediately when they are created.
Therefore, we should avoid reprocessing them when handling their parent
block later.

---------

Co-authored-by: Matt Arsenault &lt;arsenm2@gmail.com&gt;</content>
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<pre>
PHI operands and results must belong to the same register class.
If a PHI node produces an SGPR, but one of its operands is a VGPR, we
insert a VGPR-to-SGPR copy in the operand’s source block. The PHI
operand is then updated to use the destination register of the inserted
copy.

These inserted copies are processed immediately when they are created.
Therefore, we should avoid reprocessing them when handling their parent
block later.

---------

Co-authored-by: Matt Arsenault &lt;arsenm2@gmail.com&gt;</pre>
</div>
</content>
</entry>
<entry>
<title>AMDGPU: Move insertion into V2SCopies map (#130776)</title>
<updated>2025-03-18T16:28:49+00:00</updated>
<author>
<name>Matt Arsenault</name>
<email>Matthew.Arsenault@amd.com</email>
</author>
<published>2025-03-18T16:28:49+00:00</published>
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<id>dea5aa73fa1984eddde14308803bdfca56f2bc14</id>
<content type='text'>
Insert the start instruction directly into the map before the uses. This
prevents improperly re-visting sgpr-&gt;vgpr phi inputs multiple times
which
would trigger a use after free.

I don't particularly trust the iteration scheme here. This is also
unnecessarily revisting transitive users of a phi or reg_sequence for
every
input operand, but I will address that separately.

Fixes #130646. I also believe it fixes #130119, although that test fails
less consistently for me.</content>
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<pre>
Insert the start instruction directly into the map before the uses. This
prevents improperly re-visting sgpr-&gt;vgpr phi inputs multiple times
which
would trigger a use after free.

I don't particularly trust the iteration scheme here. This is also
unnecessarily revisting transitive users of a phi or reg_sequence for
every
input operand, but I will address that separately.

Fixes #130646. I also believe it fixes #130119, although that test fails
less consistently for me.</pre>
</div>
</content>
</entry>
<entry>
<title>PeepholeOpt: Do not add subregister indexes to reg_sequence operands (#124111)</title>
<updated>2025-01-30T13:42:02+00:00</updated>
<author>
<name>Matt Arsenault</name>
<email>Matthew.Arsenault@amd.com</email>
</author>
<published>2025-01-30T13:42:02+00:00</published>
<link rel='alternate' type='text/html' href='https://git.belthelziquor.com/llvm-project.git/commit/?id=d246cc618adc52fdbd69d44a2a375c8af97b6106'/>
<id>d246cc618adc52fdbd69d44a2a375c8af97b6106</id>
<content type='text'>
Given the rest of the pass just gives up when it needs to compose
subregisters, folding a subregister extract directly into a reg_sequence
is counterproductive. Later fold attempts in the function will give up
on the subregister operand, preventing looking up through the reg_sequence.

It may still be profitable to do these folds if we start handling
the composes. There are some test regressions, but this mostly
looks better.</content>
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<pre>
Given the rest of the pass just gives up when it needs to compose
subregisters, folding a subregister extract directly into a reg_sequence
is counterproductive. Later fold attempts in the function will give up
on the subregister operand, preventing looking up through the reg_sequence.

It may still be profitable to do these folds if we start handling
the composes. There are some test regressions, but this mostly
looks better.</pre>
</div>
</content>
</entry>
<entry>
<title> Reapply [AMDGPU] prevent shrinking udiv/urem if either operand exceeds signed max (#119325)</title>
<updated>2024-12-12T20:24:34+00:00</updated>
<author>
<name>choikwa</name>
<email>5455710+choikwa@users.noreply.github.com</email>
</author>
<published>2024-12-12T20:24:34+00:00</published>
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<id>463e93b95f0887145b51edb81b770eeb4463abc5</id>
<content type='text'>
This reverts commit 254d206ee2a337cb38ba347c896f7c6a14c7f218.

+Added a fix in ExpandDivRem24 to disqualify if DivNumBits exceed 24.

Original commit &amp; msg:
ce6e955ac374f2b86cbbb73b2f32174dffd85f25.
Handle signed and unsigned path differently in getDivNumBits. Using
computeKnownBits, this rejects shrinking unsigned div/rem if operands
exceed signed max since we know NumSignBits will be always 0.</content>
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<pre>
This reverts commit 254d206ee2a337cb38ba347c896f7c6a14c7f218.

+Added a fix in ExpandDivRem24 to disqualify if DivNumBits exceed 24.

Original commit &amp; msg:
ce6e955ac374f2b86cbbb73b2f32174dffd85f25.
Handle signed and unsigned path differently in getDivNumBits. Using
computeKnownBits, this rejects shrinking unsigned div/rem if operands
exceed signed max since we know NumSignBits will be always 0.</pre>
</div>
</content>
</entry>
<entry>
<title>Revert "Reapply "[AMDGPU] prevent shrinking udiv/urem if either operand is in… (#118928)"</title>
<updated>2024-12-09T14:10:49+00:00</updated>
<author>
<name>Joseph Huber</name>
<email>huberjn@outlook.com</email>
</author>
<published>2024-12-09T14:10:49+00:00</published>
<link rel='alternate' type='text/html' href='https://git.belthelziquor.com/llvm-project.git/commit/?id=254d206ee2a337cb38ba347c896f7c6a14c7f218'/>
<id>254d206ee2a337cb38ba347c896f7c6a14c7f218</id>
<content type='text'>
This reverts commit 509893b58ff444a6f080946bd368e9bde7668f13.

This broke the libc build again https://lab.llvm.org/buildbot/#/builders/73/builds/9787.
</content>
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<pre>
This reverts commit 509893b58ff444a6f080946bd368e9bde7668f13.

This broke the libc build again https://lab.llvm.org/buildbot/#/builders/73/builds/9787.
</pre>
</div>
</content>
</entry>
<entry>
<title>Reapply "[AMDGPU] prevent shrinking udiv/urem if either operand is in… (#118928)</title>
<updated>2024-12-07T00:14:39+00:00</updated>
<author>
<name>choikwa</name>
<email>5455710+choikwa@users.noreply.github.com</email>
</author>
<published>2024-12-07T00:14:39+00:00</published>
<link rel='alternate' type='text/html' href='https://git.belthelziquor.com/llvm-project.git/commit/?id=509893b58ff444a6f080946bd368e9bde7668f13'/>
<id>509893b58ff444a6f080946bd368e9bde7668f13</id>
<content type='text'>
… (SignedMax,UnsignedMax] (#116733)"

This reverts commit 905e831f8c8341e53e7e3adc57fd20b8e08eb999.

Handle signed and unsigned path differently in getDivNumBits. Using
computeKnownBits, this rejects shrinking unsigned div/rem if operands
exceed signed max since we know NumSignBits will be always 0.

Rebased and re-attempt after first one was reverted due to unrelated
failure in LibC (should be fixed by now I'm told).</content>
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<pre>
… (SignedMax,UnsignedMax] (#116733)"

This reverts commit 905e831f8c8341e53e7e3adc57fd20b8e08eb999.

Handle signed and unsigned path differently in getDivNumBits. Using
computeKnownBits, this rejects shrinking unsigned div/rem if operands
exceed signed max since we know NumSignBits will be always 0.

Rebased and re-attempt after first one was reverted due to unrelated
failure in LibC (should be fixed by now I'm told).</pre>
</div>
</content>
</entry>
<entry>
<title>Revert "[AMDGPU] prevent shrinking udiv/urem if either operand is in (SignedMax,UnsignedMax] (#116733)"</title>
<updated>2024-11-21T00:21:10+00:00</updated>
<author>
<name>Joseph Huber</name>
<email>huberjn@outlook.com</email>
</author>
<published>2024-11-21T00:15:04+00:00</published>
<link rel='alternate' type='text/html' href='https://git.belthelziquor.com/llvm-project.git/commit/?id=905e831f8c8341e53e7e3adc57fd20b8e08eb999'/>
<id>905e831f8c8341e53e7e3adc57fd20b8e08eb999</id>
<content type='text'>
This reverts commit b8e1d4dbea8905e48d51a70bf75cb8fababa4a60.

Causes failures on the `libc` test suite https://lab.llvm.org/buildbot/#/builders/73/builds/8871
</content>
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<pre>
This reverts commit b8e1d4dbea8905e48d51a70bf75cb8fababa4a60.

Causes failures on the `libc` test suite https://lab.llvm.org/buildbot/#/builders/73/builds/8871
</pre>
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</content>
</entry>
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