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<title>llvm-project.git/llvm/lib/Transforms/Scalar/LoopStrengthReduce.cpp, branch main</title>
<subtitle>Unnamed repository; edit this file 'description' to name the repository.
</subtitle>
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<entry>
<title>[LSR] Don't count conditional loads/store as enabling pre/post-index (#159573)</title>
<updated>2025-10-30T13:53:15+00:00</updated>
<author>
<name>John Brawn</name>
<email>john.brawn@arm.com</email>
</author>
<published>2025-10-30T13:53:15+00:00</published>
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<id>53e7443e0c0db82fa82d7b9009bbc5cdac1c9fac</id>
<content type='text'>
When a load/store is conditionally executed in a loop it isn't a
candidate for pre/post-index addressing, as the increment of the address
would only happen on those loop iterations where the load/store is
executed.

Detect this and only discount the AddRec cost when the load/store is
unconditional.</content>
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<pre>
When a load/store is conditionally executed in a loop it isn't a
candidate for pre/post-index addressing, as the increment of the address
would only happen on those loop iterations where the load/store is
executed.

Detect this and only discount the AddRec cost when the load/store is
unconditional.</pre>
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</content>
</entry>
<entry>
<title>[LSR] Add an addressing mode that considers all addressing modes (#158110)</title>
<updated>2025-09-16T10:46:54+00:00</updated>
<author>
<name>John Brawn</name>
<email>john.brawn@arm.com</email>
</author>
<published>2025-09-16T10:46:54+00:00</published>
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<content type='text'>
The way that loops strength reduction works is that the target has to
upfront decide whether it wants its addressing to be preindex,
postindex, or neither. This choice affects:
 * Which potential solutions we generate
* Whether we consider a pre/post index load/store as costing an AddRec
or not.

None of these choices are a good fit for either AArch64 or ARM, where
both preindex and postindex addressing are typically free:
* If we pick None then we count pre/post index addressing as costing one
addrec more than is correct so we don't pick them when we should.
* If we pick PreIndexed or PostIndexed then we get the correct cost for
that addressing type, but still get it wrong for the other and also
exclude potential solutions using offset addressing that could have less
cost.

This patch adds an "all" addressing mode that causes all potential
solutions to be generated and counts both pre and postindex as having
AddRecCost of zero. Unfortuntely this reveals problems elsewhere in how
we calculate the cost of things that need to be fixed before we can make
use of it.</content>
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<div xmlns='http://www.w3.org/1999/xhtml'>
<pre>
The way that loops strength reduction works is that the target has to
upfront decide whether it wants its addressing to be preindex,
postindex, or neither. This choice affects:
 * Which potential solutions we generate
* Whether we consider a pre/post index load/store as costing an AddRec
or not.

None of these choices are a good fit for either AArch64 or ARM, where
both preindex and postindex addressing are typically free:
* If we pick None then we count pre/post index addressing as costing one
addrec more than is correct so we don't pick them when we should.
* If we pick PreIndexed or PostIndexed then we get the correct cost for
that addressing type, but still get it wrong for the other and also
exclude potential solutions using offset addressing that could have less
cost.

This patch adds an "all" addressing mode that causes all potential
solutions to be generated and counts both pre and postindex as having
AddRecCost of zero. Unfortuntely this reveals problems elsewhere in how
we calculate the cost of things that need to be fixed before we can make
use of it.</pre>
</div>
</content>
</entry>
<entry>
<title>[Scalar] Remove an unnecessary cast (NFC) (#150474)</title>
<updated>2025-07-24T22:50:00+00:00</updated>
<author>
<name>Kazu Hirata</name>
<email>kazu@google.com</email>
</author>
<published>2025-07-24T22:50:00+00:00</published>
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<id>8b8b0f197fc66a3495722eca15cd807f5aa1769a</id>
<content type='text'>
getOperand() already returns Value *.</content>
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<pre>
getOperand() already returns Value *.</pre>
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</content>
</entry>
<entry>
<title>[LSR] Do not consider uses in lifetime intrinsics (#149492)</title>
<updated>2025-07-18T14:13:00+00:00</updated>
<author>
<name>Nikita Popov</name>
<email>npopov@redhat.com</email>
</author>
<published>2025-07-18T14:13:00+00:00</published>
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<id>5f531827a4b90f6e0051056fffd8642ae1c677e6</id>
<content type='text'>
We should ignore uses of pointers in lifetime intrinsics, as these are
not actually materialized in the final code, so don't affect register
pressure or anything else LSR needs to model.
    
Handling these only results in peculiar rewrites where additional
intermediate GEPs are introduced.</content>
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<pre>
We should ignore uses of pointers in lifetime intrinsics, as these are
not actually materialized in the final code, so don't affect register
pressure or anything else LSR needs to model.
    
Handling these only results in peculiar rewrites where additional
intermediate GEPs are introduced.</pre>
</div>
</content>
</entry>
<entry>
<title>[DebugInfo] Suppress lots of users of DbgValueInst (#149476)</title>
<updated>2025-07-18T10:31:52+00:00</updated>
<author>
<name>Jeremy Morse</name>
<email>jeremy.morse@sony.com</email>
</author>
<published>2025-07-18T10:31:52+00:00</published>
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<id>c9d8b68676dbf51996a76475313088f750697343</id>
<content type='text'>
This is another prune of dead code -- we never generate debug intrinsics
nowadays, therefore there's no need for these codepaths to run.

---------

Co-authored-by: Nikita Popov &lt;github@npopov.com&gt;</content>
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<pre>
This is another prune of dead code -- we never generate debug intrinsics
nowadays, therefore there's no need for these codepaths to run.

---------

Co-authored-by: Nikita Popov &lt;github@npopov.com&gt;</pre>
</div>
</content>
</entry>
<entry>
<title>[DebugInfo][RemoveDIs] Suppress getNextNonDebugInfoInstruction (#144383)</title>
<updated>2025-07-15T14:34:10+00:00</updated>
<author>
<name>Jeremy Morse</name>
<email>jeremy.morse@sony.com</email>
</author>
<published>2025-07-15T14:34:10+00:00</published>
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<id>57a5f9c47e063701ac7d13a5efd993e839e148eb</id>
<content type='text'>
There are no longer debug-info instructions, thus we don't need this
skipping. Horray!</content>
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<pre>
There are no longer debug-info instructions, thus we don't need this
skipping. Horray!</pre>
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</content>
</entry>
<entry>
<title>[LSR] Account for hardware loop instructions (#147958)</title>
<updated>2025-07-14T15:48:54+00:00</updated>
<author>
<name>John Brawn</name>
<email>john.brawn@arm.com</email>
</author>
<published>2025-07-14T15:48:54+00:00</published>
<link rel='alternate' type='text/html' href='https://git.belthelziquor.com/llvm-project.git/commit/?id=f8c2c4f161a6a98f623a6263a248fb24927eeaec'/>
<id>f8c2c4f161a6a98f623a6263a248fb24927eeaec</id>
<content type='text'>
A hardware loop instruction combines a subtract, compare with zero, and
branch. We currently account for the compare and branch being combined
into one in Cost::RateFormula, as part of more general handling for
compare-branch-zero, but don't account for the subtract, leading to
suboptimal decisions in some cases.

Fix this in Cost::RateRegister by noticing when we have such a subtract
and discounting the AddRecCost in such a case.</content>
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<pre>
A hardware loop instruction combines a subtract, compare with zero, and
branch. We currently account for the compare and branch being combined
into one in Cost::RateFormula, as part of more general handling for
compare-branch-zero, but don't account for the subtract, leading to
suboptimal decisions in some cases.

Fix this in Cost::RateRegister by noticing when we have such a subtract
and discounting the AddRecCost in such a case.</pre>
</div>
</content>
</entry>
<entry>
<title>[DebugInfo][LoopStrengthReduce] Salvage the debug value of the dead cmp instruction (#147241)</title>
<updated>2025-07-14T01:45:37+00:00</updated>
<author>
<name>Shan Huang</name>
<email>shan.huang@stu.ecnu.edu.cn</email>
</author>
<published>2025-07-14T01:45:37+00:00</published>
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<id>089106fdfb853c83cf5d35a37bdd8e663094e6a2</id>
<content type='text'>
Fix #147238</content>
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<pre>
Fix #147238</pre>
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</content>
</entry>
<entry>
<title>[LSR] Strip dead code (NFC) (#146109)</title>
<updated>2025-07-03T12:37:08+00:00</updated>
<author>
<name>Ramkumar Ramachandra</name>
<email>ramkumar.ramachandra@codasip.com</email>
</author>
<published>2025-07-03T12:37:08+00:00</published>
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<id>b7059ebafe8a8f6ff2c20a93701ccbd6e009be79</id>
<content type='text'>
Nested AddRec is already rejected by the handling in pushSCEV().</content>
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<pre>
Nested AddRec is already rejected by the handling in pushSCEV().</pre>
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</content>
</entry>
<entry>
<title>[LSR] Clean up code using SCEVPatternMatch (NFC) (#145556)</title>
<updated>2025-06-28T10:41:53+00:00</updated>
<author>
<name>Ramkumar Ramachandra</name>
<email>ramkumar.ramachandra@codasip.com</email>
</author>
<published>2025-06-28T10:41:53+00:00</published>
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</content>
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<pre>
</pre>
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