llvm-project.git/llvm/lib/TargetParser/RISCVISAInfo.cpp, branch users/chapuni/cov/single/condop Unnamed repository; edit this file 'description' to name the repository. [RISCV] Add Qualcomm uC Xqcicm (Conditional Move) extension (#121752) 2025-01-07T02:55:00+00:00 quic_hchandel 165007698+hchandel@users.noreply.github.com 2025-01-07T02:55:00+00:00 737d6ca44d383bcf33a0605a7d9014027296269a The Qualcomm uC Xqcicm extension adds 13 conditional move instructions. The current spec can be found at: https://github.com/quic/riscv-unified-db/releases/latest This patch adds assembler only support. --------- Co-authored-by: Harsh Chandel <hchandel@qti.qualcomm.com> 
The Qualcomm uC Xqcicm extension adds 13 conditional move instructions.

The current spec can be found at:
https://github.com/quic/riscv-unified-db/releases/latest

This patch adds assembler only support.

---------

Co-authored-by: Harsh Chandel <hchandel@qti.qualcomm.com>
 [RISCV] Add Qualcomm uC Xqcicli (Conditional Load Immediate) extension (#121292) 2025-01-03T01:03:27+00:00 Sudharsan Veeravalli quic_svs@quicinc.com 2025-01-03T01:03:27+00:00 532a2691bc015fafdd356c10b17c466fe28c49b1 This extension adds 12 instructions that conditionally load an immediate value. The current spec can be found at: https://github.com/quic/riscv-unified-db/releases/latest This patch adds assembler only support. 
This extension adds 12 instructions that conditionally load an immediate
value.

The current spec can be found at:
https://github.com/quic/riscv-unified-db/releases/latest

This patch adds assembler only support.
 [RISCV] Add Qualcomm uC Xqciac (Load-Store Adress calculation) extension (#121037) 2024-12-29T05:44:12+00:00 quic_hchandel 165007698+hchandel@users.noreply.github.com 2024-12-29T05:44:12+00:00 1557eeda738d7dbe51d2f52fce28a1fd6f5844ce This extension adds 3 instructions that perform load-store address calculation. The current spec can be found at: https://github.com/quic/riscv-unified-db/releases/latest This patch adds assembler only support. --------- Co-authored-by: Harsh Chandel <hchandel@qti.qualcomm.com> Co-authored-by: Sudharsan Veeravalli <quic_svs@quicinc.com> 
This extension adds 3 instructions that perform load-store address
calculation.

The current spec can be found at:
https://github.com/quic/riscv-unified-db/releases/latest

This patch adds assembler only support.

---------

Co-authored-by: Harsh Chandel <hchandel@qti.qualcomm.com>
Co-authored-by: Sudharsan Veeravalli <quic_svs@quicinc.com>
 [RISCV] Add Qualcomm uC Xqcilsm (Load Store Multiple) extension (#119823) 2024-12-13T18:36:58+00:00 Sudharsan Veeravalli quic_svs@quicinc.com 2024-12-13T18:36:58+00:00 668d9688ac8aa97d9156cecabd25bf2a8e82bc9d This extension adds 6 instructions that can do multi-word load/store. The current spec can be found at: https://github.com/quic/riscv-unified-db/releases/latest This patch adds assembler only support. 
This extension adds 6 instructions that can do multi-word load/store.

The current spec can be found at:
https://github.com/quic/riscv-unified-db/releases/latest

This patch adds assembler only support.
 [RISCV] Add Qualcomm uC Xqcics(Conditional Select) extension (#119504) 2024-12-12T05:42:09+00:00 quic_hchandel 165007698+hchandel@users.noreply.github.com 2024-12-12T05:42:09+00:00 0614c601b44ca2f214a9868a8b672ea695d5d56a The Qualcomm uC Xqcics extension adds 8 conditional select instructions. The current spec can be found at: https://github.com/quic/riscv-unified-db/releases/latest This patch adds assembler only support. --------- Co-authored-by: Harsh Chandel <hchandel@qti.qualcomm.com> 
The Qualcomm uC Xqcics extension adds 8 conditional select instructions.

The current spec can be found at:
https://github.com/quic/riscv-unified-db/releases/latest

This patch adds assembler only support.

---------

Co-authored-by: Harsh Chandel <hchandel@qti.qualcomm.com>
 [RISCV] Add Qualcomm uC Xqcia (Arithmetic) extension (#118113) 2024-12-01T11:36:22+00:00 Sudharsan Veeravalli quic_svs@quicinc.com 2024-12-01T11:36:22+00:00 6881c6d2a6ef2b9f1736afb124b2486d6b8bc603 This extension adds 11 instructions that perform integer arithmetic. The current spec can be found at: https://github.com/quic/riscv-unified-db/releases/latest This patch adds assembler only support. 
This extension adds 11 instructions that perform integer arithmetic.

The current spec can be found at:
https://github.com/quic/riscv-unified-db/releases/latest

This patch adds assembler only support.
 [RISCV] Add Qualcomm uC Xqcisls (Scaled Load Store) extension (#117987) 2024-11-29T04:56:00+00:00 Sudharsan Veeravalli quic_svs@quicinc.com 2024-11-29T04:56:00+00:00 8fcbba82d6c8038c4a0c5859275523414107b198 This extension adds 8 load/store instructions with a scaled index addressing mode. The current spec can be found at: https://github.com/quic/riscv-unified-db/releases/latest This patch adds assembler only support. 
This extension adds 8 load/store instructions with a scaled index
addressing mode.

The current spec can be found at:
https://github.com/quic/riscv-unified-db/releases/latest

This patch adds assembler only support.
 [RISCV] Add Qualcomm uC Xqcicsr (CSR) extension (#117169) 2024-11-28T07:16:15+00:00 Sudharsan Veeravalli quic_svs@quicinc.com 2024-11-28T07:16:15+00:00 c4645ffedacad18e4cd1dd372288aa55178b1c44 The Qualcomm uC Xqcicsr extension adds 2 instructions that can read and write CSRs. The current spec can be found at: https://github.com/quic/riscv-unified-db/releases/latest This patch adds assembler only support. 
The Qualcomm uC Xqcicsr extension adds 2 instructions that can read and
write CSRs.

The current spec can be found at:
https://github.com/quic/riscv-unified-db/releases/latest

This patch adds assembler only support.
 [RISCV] Zabha/Zacas implies Zaamo (#115694) 2024-11-12T07:49:34+00:00 Jim Lin jim@andestech.com 2024-11-12T07:49:34+00:00 956361ca080a689a96b6552d28681aaf0ad2f494 The Zabha/Zacas extension depends upon the Zaamo extension. Ref: https://github.com/riscv/riscv-isa-manual/blob/main/src/zacas.adoc https://github.com/riscv/riscv-isa-manual/blob/main/src/zabha.adoc. 
The Zabha/Zacas extension depends upon the Zaamo extension. 
Ref: https://github.com/riscv/riscv-isa-manual/blob/main/src/zacas.adoc
https://github.com/riscv/riscv-isa-manual/blob/main/src/zabha.adoc.
 [RISCV] Remove Zvk* dependency checks from RISCVISAInfo::checkDependency. 2024-10-29T20:57:23+00:00 Craig Topper craig.topper@sifive.com 2024-10-29T20:50:41+00:00 94e7d9c0bfe517507ea08b00fb00c32fb2837a82 The Zvk* extensions now imply Zve32x or Zve64x so it shouldn't be possible to fail these dependency checks. 
The Zvk* extensions now imply Zve32x or Zve64x so it shouldn't be
possible to fail these dependency checks.