llvm-project.git/llvm/lib/Target, branch users/mingmingl-llvm/samplefdo-profile-format Unnamed repository; edit this file 'description' to name the repository. [AMDGPU] Restrict operands of ld_scale_paired to low 256 vgprs. NFCI (#157935) 2025-09-10T22:17:55+00:00 Stanislav Mekhanoshin Stanislav.Mekhanoshin@amd.com 2025-09-10T22:17:55+00:00 b8cefcb601ddaa18482555c4ff363c01a270c2fe This is NFC because these instructions are never selected just by itself. 
This is NFC because these instructions are never selected just
by itself.
 [RISCV] Correct the predicate for the ror and rorw with immediate InstAliases. (#157921) 2025-09-10T19:20:27+00:00 Craig Topper craig.topper@sifive.com 2025-09-10T19:20:27+00:00 d7e6e7289d668354e63c48fd229198ae697f8521 






[RISCV][GISel] Widen G_ABDS/G_ABDU before lowering when Zbb is enabled. (#157766)
2025-09-10T19:17:30+00:00

Craig Topper
craig.topper@sifive.com

2025-09-10T19:17:30+00:00

262c7b7b5a996b0c46fdfc3480273f1864edc1c0

This allows us to use G_SMIN/SMAX/UMIN/UMAX in the lowering.




This allows us to use G_SMIN/SMAX/UMIN/UMAX in the lowering.






[RISCV] Add helper method for detecting BEXTI or TH_TST is supported. NFC (#157915)
2025-09-10T19:16:46+00:00

Craig Topper
craig.topper@sifive.com

2025-09-10T19:16:46+00:00

c6947dad53dacc19d47b4da6b1984ca39ec111f6

These instructions both extract single bit to bit 0 and fill the upper
bits with 0.

There's at least one place where we check for BEXTI but not TH_TST. I
wanted to keep this patch NFC so that will be a follow up fix.




These instructions both extract single bit to bit 0 and fill the upper
bits with 0.

There's at least one place where we check for BEXTI but not TH_TST. I
wanted to keep this patch NFC so that will be a follow up fix.






[DirectX] Removing dxbc DescriptorRange from mcbxdc (#154629)
2025-09-10T18:49:01+00:00

joaosaffran
joaosaffranllvm@gmail.com

2025-09-10T18:49:01+00:00

9e778f6cd155f64896a9a0580e96aa4814ca999b

MC Descriptor Range Representation currently depend on Object
structures. This PR removes that dependency and in order to facilitate
removing to_underlying usage in follow-up PRs.




MC Descriptor Range Representation currently depend on Object
structures. This PR removes that dependency and in order to facilitate
removing to_underlying usage in follow-up PRs.






[RISCV] Fix mistake in comment in RISCVInstrInfoP.td. NFC
2025-09-10T17:38:15+00:00

Craig Topper
craig.topper@sifive.com

2025-09-10T17:38:15+00:00

ebf86b1c28d9e358403fe2b1bd145f339806799a












[RISCV] Extend zvqdot matching to handle disjoint or (#157901)
2025-09-10T17:27:51+00:00

Hongyu Chen
xxs_chy@outlook.com

2025-09-10T17:27:51+00:00

33c9236bf870bc732a48a0256e90b907d1c21a49

This patch makes use of pattern matching to handle disjoint or. Also, it
simplifies the multiplication matching.




This patch makes use of pattern matching to handle disjoint or. Also, it
simplifies the multiplication matching.






[RISCV] Add helper method for checking for Zicond or XVentanaCondOps. NFC (#157891)
2025-09-10T17:24:47+00:00

Craig Topper
craig.topper@sifive.com

2025-09-10T17:24:47+00:00

b580829c2b16de0b22716b3f9b9a9b2e79c55af5

These two extensions have identical functionality so we always want to
treat them the same.




These two extensions have identical functionality so we always want to
treat them the same.






AMDGPU/UniformityAnalysis: fix G_ZEXTLOAD and G_SEXTLOAD (#157845)
2025-09-10T15:57:15+00:00

Petar Avramovic
Petar.Avramovic@amd.com

2025-09-10T15:57:15+00:00

41c685975e17704b25e461744ebd57429cdd95f1

Use same rules for G_ZEXTLOAD and G_SEXTLOAD as for G_LOAD.
Flat addrspace(0) and private addrspace(5) G_ZEXTLOAD and G_SEXTLOAD
should be always divergent.




Use same rules for G_ZEXTLOAD and G_SEXTLOAD as for G_LOAD.
Flat addrspace(0) and private addrspace(5) G_ZEXTLOAD and G_SEXTLOAD
should be always divergent.






[RISCV] Fold (X & -(1 << C1) & 0xffffffff) == C2 << C1 to sraiw X, C1 == C2. (#157617)
2025-09-10T15:51:47+00:00

Craig Topper
craig.topper@sifive.com

2025-09-10T15:51:47+00:00

61e4d2312d59d059f775734a3a7c96a6914c07b7

We had an existing fold for (X & -(1 << C1) & 0xffffffff) == 0
which we can generalize to support comparing to constants other
than 0.
    
Previously we used srliw, but this generalizes better using sraiw.
I'm restricting to the case where C2 is simm12 or 2048 to allow
sraiw+addi/xori+seqz/snez to be used. Other constants require a
more careful analysis of the constants involved.




We had an existing fold for (X & -(1 << C1) & 0xffffffff) == 0
which we can generalize to support comparing to constants other
than 0.
    
Previously we used srliw, but this generalizes better using sraiw.
I'm restricting to the case where C2 is simm12 or 2048 to allow
sraiw+addi/xori+seqz/snez to be used. Other constants require a
more careful analysis of the constants involved.