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<title>llvm-project.git/llvm/lib/Target/XCore/XCoreInstrInfo.cpp, branch main</title>
<subtitle>Unnamed repository; edit this file 'description' to name the repository.
</subtitle>
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<entry>
<title>CodeGen: Remove TRI arguments from stack load/store hooks (#158240)</title>
<updated>2025-11-11T00:24:39+00:00</updated>
<author>
<name>Matt Arsenault</name>
<email>Matthew.Arsenault@amd.com</email>
</author>
<published>2025-11-11T00:24:39+00:00</published>
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<id>1f3f522866ae483836cd39c13695a0ab41b547d5</id>
<content type='text'>
This is directly available in TargetInstrInfo</content>
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<pre>
This is directly available in TargetInstrInfo</pre>
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</entry>
<entry>
<title>CodeGen: Keep reference to TargetRegisterInfo in TargetInstrInfo (#158224)</title>
<updated>2025-11-10T22:40:39+00:00</updated>
<author>
<name>Matt Arsenault</name>
<email>Matthew.Arsenault@amd.com</email>
</author>
<published>2025-11-10T22:40:39+00:00</published>
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<id>11ab23c33db5c990489023c91260435db288efd8</id>
<content type='text'>
Both conceptually belong to the same subtarget, so it should not
be necessary to pass in the context TargetRegisterInfo to any
TargetInstrInfo member. Add this reference so those superfluous
arguments can be removed.

Most targets placed their TargetRegisterInfo as a member
in TargetInstrInfo. A few had this owned by the TargetSubtargetInfo,
so unify all targets to look the same.</content>
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<pre>
Both conceptually belong to the same subtarget, so it should not
be necessary to pass in the context TargetRegisterInfo to any
TargetInstrInfo member. Add this reference so those superfluous
arguments can be removed.

Most targets placed their TargetRegisterInfo as a member
in TargetInstrInfo. A few had this owned by the TargetSubtargetInfo,
so unify all targets to look the same.</pre>
</div>
</content>
</entry>
<entry>
<title>CodeGen: Pass SubtargetInfo to TargetGenInstrInfo constructors (#157337)</title>
<updated>2025-09-08T03:12:19+00:00</updated>
<author>
<name>Matt Arsenault</name>
<email>Matthew.Arsenault@amd.com</email>
</author>
<published>2025-09-08T03:12:19+00:00</published>
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<id>727e9f5ea5b2bb9d2fa37619ad2f19b21af7ce4d</id>
<content type='text'>
This will make it possible for tablegen to make subtarget
dependent decisions without adding new arguments to every
target.

---------

Co-authored-by: Sergei Barannikov &lt;barannikov88@gmail.com&gt;</content>
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<pre>
This will make it possible for tablegen to make subtarget
dependent decisions without adding new arguments to every
target.

---------

Co-authored-by: Sergei Barannikov &lt;barannikov88@gmail.com&gt;</pre>
</div>
</content>
</entry>
<entry>
<title>Revert "[X86][ARM][RISCV][XCore][M68K] Invert the low bit to get the inverse predicate (NFC) (#151748)"</title>
<updated>2025-08-04T22:24:52+00:00</updated>
<author>
<name>Craig Topper</name>
<email>craig.topper@sifive.com</email>
</author>
<published>2025-08-04T22:24:16+00:00</published>
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<id>f58bc72759e2e6e11d7e50ef3370a5a7d345e651</id>
<content type='text'>
This reverts commit 518703806286c98bac7b84156738839f8bd55bef.

Failing M68k build bot.
</content>
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<pre>
This reverts commit 518703806286c98bac7b84156738839f8bd55bef.

Failing M68k build bot.
</pre>
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</content>
</entry>
<entry>
<title>[X86][ARM][RISCV][XCore][M68K] Invert the low bit to get the inverse predicate (NFC) (#151748)</title>
<updated>2025-08-04T21:45:04+00:00</updated>
<author>
<name>AZero13</name>
<email>gfunni234@gmail.com</email>
</author>
<published>2025-08-04T21:45:04+00:00</published>
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<id>518703806286c98bac7b84156738839f8bd55bef</id>
<content type='text'>
All these platforms defined their predicate in such a way to allow bit
twiddling to get inverse predicates</content>
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<pre>
All these platforms defined their predicate in such a way to allow bit
twiddling to get inverse predicates</pre>
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</content>
</entry>
<entry>
<title>[CodeGen] Change copyPhysReg interface to use Register instead of MCRegister. (#128473)</title>
<updated>2025-02-24T17:55:34+00:00</updated>
<author>
<name>Craig Topper</name>
<email>craig.topper@sifive.com</email>
</author>
<published>2025-02-24T17:55:34+00:00</published>
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<id>571b787b83cb1bfc7d4c8214b296ec965e7bb7e2</id>
<content type='text'>
NVPTX, SPIRV, and WebAssembly pass virtual registers to this function
since they don't perform register allocation. We need to use Register to
avoid a virtual register being converted to MCRegister by the caller.</content>
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<pre>
NVPTX, SPIRV, and WebAssembly pass virtual registers to this function
since they don't perform register allocation. We need to use Register to
avoid a virtual register being converted to MCRegister by the caller.</pre>
</div>
</content>
</entry>
<entry>
<title>[llvm] Pass MachineInstr flags to storeRegToStackSlot/loadRegFromStackSlot (NFC) (#120622)</title>
<updated>2025-01-22T08:06:39+00:00</updated>
<author>
<name>Venkata Ramanaiah Nalamothu</name>
<email>quic_vnalamot@quicinc.com</email>
</author>
<published>2025-01-22T08:06:39+00:00</published>
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<id>f7d8336a2fb4fad4a6efe5af9b0a10ddd970f6d3</id>
<content type='text'>
This patch is in preparation to enable setting the MachineInstr::MIFlag
flags, i.e. FrameSetup/FrameDestroy, on callee saved register
spill/reload instructions in prologue/epilogue. This eventually helps in
setting the prologue_end and epilogue_begin markers more accurately.

The DWARF Spec in "6.4 Call Frame Information" says:

The code that allocates space on the call frame stack and performs the
save
operation is called the subroutine’s prologue, and the code that
performs
the restore operation and deallocates the frame is called its epilogue.

which means the callee saved register spills and reloads are part of
prologue (a.k.a frame setup) and epilogue (a.k.a frame destruction),
respectively. And, IIUC, LLVM backend uses FrameSetup/FrameDestroy flags
to identify instructions that are part of call frame setup and
destruction.

In the trunk, while most targets consistently set
FrameSetup/FrameDestroy on save/restore call frame information (CFI)
instructions of callee saved registers, they do not consistently set
those flags on the actual callee saved register spill/reload
instructions.

I believe this patch provides a clean mechanism to set
FrameSetup/FrameDestroy flags on the actual callee saved register
spill/reload instructions as needed. And, by having default argument of
MachineInstr::NoFlags for Flags, this patch is a NFC.

With this patch, the targets have to just pass FrameSetup/FrameDestroy
flag to the storeRegToStackSlot/loadRegFromStackSlot calls from the
target derived spillCalleeSavedRegisters and restoreCalleeSavedRegisters
to set those flags on callee saved register spill/reload instructions.

Also, this patch makes it very easy to set the source line information
on callee saved register spill/reload instructions which is needed by
the DwarfDebug.cpp implementation to set prologue_end and epilogue_begin
markers more accurately.

As per DwarfDebug.cpp implementation:

prologue_end is the first known non-DBG_VALUE and non-FrameSetup
location
    that marks the beginning of the function body

epilogue_begin is the first FrameDestroy location that has been seen in
the
    epilogue basic block

With this patch, the targets have to just do the following to set the
source line information on callee saved register spill/reload
instructions, without hampering the LLVM's efforts to avoid adding
source line information on the artificial code generated by the
compiler.

    &lt;Foo&gt;InstrInfo::storeRegToStackSlot() {
    ...
      DebugLoc DL =
Flags &amp; MachineInstr::FrameSetup ? DebugLoc() : MBB.findDebugLoc(I);
    ...
    }

    &lt;Foo&gt;InstrInfo::loadRegFromStackSlot() {
    ...
      DebugLoc DL =
Flags &amp; MachineInstr::FrameDestroy ? MBB.findDebugLoc(I) : DebugLoc();
    ...
    }

While I understand this patch would break out-of-tree backend builds, I
think it is in the right direction.

One immediate use case that can benefit from this patch is fixing
#120553 becomes simpler.</content>
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<div xmlns='http://www.w3.org/1999/xhtml'>
<pre>
This patch is in preparation to enable setting the MachineInstr::MIFlag
flags, i.e. FrameSetup/FrameDestroy, on callee saved register
spill/reload instructions in prologue/epilogue. This eventually helps in
setting the prologue_end and epilogue_begin markers more accurately.

The DWARF Spec in "6.4 Call Frame Information" says:

The code that allocates space on the call frame stack and performs the
save
operation is called the subroutine’s prologue, and the code that
performs
the restore operation and deallocates the frame is called its epilogue.

which means the callee saved register spills and reloads are part of
prologue (a.k.a frame setup) and epilogue (a.k.a frame destruction),
respectively. And, IIUC, LLVM backend uses FrameSetup/FrameDestroy flags
to identify instructions that are part of call frame setup and
destruction.

In the trunk, while most targets consistently set
FrameSetup/FrameDestroy on save/restore call frame information (CFI)
instructions of callee saved registers, they do not consistently set
those flags on the actual callee saved register spill/reload
instructions.

I believe this patch provides a clean mechanism to set
FrameSetup/FrameDestroy flags on the actual callee saved register
spill/reload instructions as needed. And, by having default argument of
MachineInstr::NoFlags for Flags, this patch is a NFC.

With this patch, the targets have to just pass FrameSetup/FrameDestroy
flag to the storeRegToStackSlot/loadRegFromStackSlot calls from the
target derived spillCalleeSavedRegisters and restoreCalleeSavedRegisters
to set those flags on callee saved register spill/reload instructions.

Also, this patch makes it very easy to set the source line information
on callee saved register spill/reload instructions which is needed by
the DwarfDebug.cpp implementation to set prologue_end and epilogue_begin
markers more accurately.

As per DwarfDebug.cpp implementation:

prologue_end is the first known non-DBG_VALUE and non-FrameSetup
location
    that marks the beginning of the function body

epilogue_begin is the first FrameDestroy location that has been seen in
the
    epilogue basic block

With this patch, the targets have to just do the following to set the
source line information on callee saved register spill/reload
instructions, without hampering the LLVM's efforts to avoid adding
source line information on the artificial code generated by the
compiler.

    &lt;Foo&gt;InstrInfo::storeRegToStackSlot() {
    ...
      DebugLoc DL =
Flags &amp; MachineInstr::FrameSetup ? DebugLoc() : MBB.findDebugLoc(I);
    ...
    }

    &lt;Foo&gt;InstrInfo::loadRegFromStackSlot() {
    ...
      DebugLoc DL =
Flags &amp; MachineInstr::FrameDestroy ? MBB.findDebugLoc(I) : DebugLoc();
    ...
    }

While I understand this patch would break out-of-tree backend builds, I
think it is in the right direction.

One immediate use case that can benefit from this patch is fixing
#120553 becomes simpler.</pre>
</div>
</content>
</entry>
<entry>
<title>[Target] Remove unused includes (NFC) (#116577)</title>
<updated>2024-11-18T15:19:50+00:00</updated>
<author>
<name>Kazu Hirata</name>
<email>kazu@google.com</email>
</author>
<published>2024-11-18T15:19:50+00:00</published>
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<id>ed8019d9fbed2e6a6b08f8f73e9fa54a24f3ed52</id>
<content type='text'>
Identified with misc-include-cleaner.</content>
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<pre>
Identified with misc-include-cleaner.</pre>
</div>
</content>
</entry>
<entry>
<title>[TII][RISCV] Add renamable bit to copyPhysReg (#91179)</title>
<updated>2024-08-27T02:08:43+00:00</updated>
<author>
<name>Piyou Chen</name>
<email>piyou.chen@sifive.com</email>
</author>
<published>2024-08-27T02:08:43+00:00</published>
<link rel='alternate' type='text/html' href='https://git.belthelziquor.com/llvm-project.git/commit/?id=b01c006f734a0977a4fd9c7f1a706c8230663739'/>
<id>b01c006f734a0977a4fd9c7f1a706c8230663739</id>
<content type='text'>
The renamable flag is useful during MachineCopyPropagation but renamable
flag will be dropped after lowerCopy in some case.

This patch introduces extra arguments to pass the renamable flag to
copyPhysReg.</content>
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<div xmlns='http://www.w3.org/1999/xhtml'>
<pre>
The renamable flag is useful during MachineCopyPropagation but renamable
flag will be dropped after lowerCopy in some case.

This patch introduces extra arguments to pass the renamable flag to
copyPhysReg.</pre>
</div>
</content>
</entry>
<entry>
<title>[TTI] Use Register in isLoadFromStackSlot and isStoreToStackSlot [nfc] (#80339)</title>
<updated>2024-02-02T01:52:35+00:00</updated>
<author>
<name>Philip Reames</name>
<email>preames@rivosinc.com</email>
</author>
<published>2024-02-02T01:52:35+00:00</published>
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<content type='text'>
</content>
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<pre>
</pre>
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</content>
</entry>
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