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<title>llvm-project.git/llvm/lib/Target/XCore/XCoreFrameLowering.cpp, branch main</title>
<subtitle>Unnamed repository; edit this file 'description' to name the repository.
</subtitle>
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<entry>
<title>CodeGen: Remove TRI arguments from stack load/store hooks (#158240)</title>
<updated>2025-11-11T00:24:39+00:00</updated>
<author>
<name>Matt Arsenault</name>
<email>Matthew.Arsenault@amd.com</email>
</author>
<published>2025-11-11T00:24:39+00:00</published>
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<id>1f3f522866ae483836cd39c13695a0ab41b547d5</id>
<content type='text'>
This is directly available in TargetInstrInfo</content>
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<pre>
This is directly available in TargetInstrInfo</pre>
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</entry>
<entry>
<title>[FrameLowering] Use MCRegister instead of Register in CalleeSavedInfo. NFC (#128095)</title>
<updated>2025-02-21T07:44:05+00:00</updated>
<author>
<name>Craig Topper</name>
<email>craig.topper@sifive.com</email>
</author>
<published>2025-02-21T07:44:05+00:00</published>
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<id>af64f0a6c2e26b3fd1979c1fa380136e5528c9b3</id>
<content type='text'>
Callee saved registers should always be phyiscal registers. They are
often passed directly to other functions that take MCRegister like
getMinimalPhysRegClass or TargetRegisterClass::contains.

Unfortunately, sometimes the MCRegister is compared to a Register which
gave an ambiguous comparison error when the MCRegister is on the LHS.
Adding a MCRegister==Register comparison operator created more ambiguous
comparison errors elsewhere. These cases were usually comparing against
a base or frame pointer register that is a physical register in a
Register. For those I added an explicit conversion of Register to
MCRegister to fix the error.</content>
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<pre>
Callee saved registers should always be phyiscal registers. They are
often passed directly to other functions that take MCRegister like
getMinimalPhysRegClass or TargetRegisterClass::contains.

Unfortunately, sometimes the MCRegister is compared to a Register which
gave an ambiguous comparison error when the MCRegister is on the LHS.
Adding a MCRegister==Register comparison operator created more ambiguous
comparison errors elsewhere. These cases were usually comparing against
a base or frame pointer register that is a physical register in a
Register. For those I added an explicit conversion of Register to
MCRegister to fix the error.</pre>
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</content>
</entry>
<entry>
<title>[llvm] Mark scavenging spill-slots as *spilled* stack objects. (#122673)</title>
<updated>2025-01-14T08:18:31+00:00</updated>
<author>
<name>Guy David</name>
<email>49722543+guy-david@users.noreply.github.com</email>
</author>
<published>2025-01-14T08:18:31+00:00</published>
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<id>1a935d7a17519e9b75d12c3caf9a54a3405a0af3</id>
<content type='text'>
This seems like an oversight when copying code from other backends.</content>
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<pre>
This seems like an oversight when copying code from other backends.</pre>
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</content>
</entry>
<entry>
<title>[Target] Remove unused includes (NFC) (#116577)</title>
<updated>2024-11-18T15:19:50+00:00</updated>
<author>
<name>Kazu Hirata</name>
<email>kazu@google.com</email>
</author>
<published>2024-11-18T15:19:50+00:00</published>
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<id>ed8019d9fbed2e6a6b08f8f73e9fa54a24f3ed52</id>
<content type='text'>
Identified with misc-include-cleaner.</content>
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<pre>
Identified with misc-include-cleaner.</pre>
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</content>
</entry>
<entry>
<title>[llvm] Consistently respect `naked` fn attribute in `TargetFrameLowering::hasFP()` (#106014)</title>
<updated>2024-10-18T05:35:42+00:00</updated>
<author>
<name>Alex Rønne Petersen</name>
<email>alex@alexrp.com</email>
</author>
<published>2024-10-18T05:35:42+00:00</published>
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<id>ad4a582fd938c933e784f0052bd773676b37b690</id>
<content type='text'>
Some targets (e.g. PPC and Hexagon) already did this. I think it's best
to do this consistently so that frontend authors don't run into
inconsistent results when they emit `naked` functions. For example, in
Zig, we had to change our emit code to also set `frame-pointer=none` to
get reliable results across targets.

Note: I don't have commit access.</content>
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<pre>
Some targets (e.g. PPC and Hexagon) already did this. I think it's best
to do this consistently so that frontend authors don't run into
inconsistent results when they emit `naked` functions. For example, in
Zig, we had to change our emit code to also set `frame-pointer=none` to
get reliable results across targets.

Note: I don't have commit access.</pre>
</div>
</content>
</entry>
<entry>
<title>CodeGen: Avoid some references to MachineFunction's getMMI (#99652)</title>
<updated>2024-07-19T18:09:05+00:00</updated>
<author>
<name>Matt Arsenault</name>
<email>Matthew.Arsenault@amd.com</email>
</author>
<published>2024-07-19T18:09:05+00:00</published>
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<id>0f0cfcff2ca65e295cd84d3eda6f8e93b76cb3a8</id>
<content type='text'>
MachineFunction's probably should not include a backreference to
the owning MachineModuleInfo. Most of these references were used
just to query the MCContext, which MachineFunction already directly
stores. Other contexts are using it to query the LLVMContext, which
can already be accessed through the IR function reference.</content>
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<pre>
MachineFunction's probably should not include a backreference to
the owning MachineModuleInfo. Most of these references were used
just to query the MCContext, which MachineFunction already directly
stores. Other contexts are using it to query the LLVMContext, which
can already be accessed through the IR function reference.</pre>
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</content>
</entry>
<entry>
<title>[CodeGen] Additional Register argument to storeRegToStackSlot/loadRegFromStackSlot</title>
<updated>2022-12-17T06:25:34+00:00</updated>
<author>
<name>Christudasan Devadasan</name>
<email>Christudasan.Devadasan@amd.com</email>
</author>
<published>2022-11-24T08:17:01+00:00</published>
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<id>b5efec4b27bf5451a4fae74973f7a7a28fbc6108</id>
<content type='text'>
With D134950, targets get notified when a virtual register is created and/or
cloned. Targets can do the needful with the delegate callback. AMDGPU propagates
the virtual register flags maintained in the target file itself. They are useful
to identify a certain type of machine operands while inserting spill stores and
reloads. Since RegAllocFast spills the physical register itself, there is no way
its virtual register can be mapped back to retrieve the flags. It can be solved
by passing the virtual register as an additional argument. This argument has no
use when the spill interfaces are called during the greedy allocator or even the
PrologEpilogInserter and can pass a null register in such cases.

Reviewed By: arsenm

Differential Revision: https://reviews.llvm.org/D138656
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<pre>
With D134950, targets get notified when a virtual register is created and/or
cloned. Targets can do the needful with the delegate callback. AMDGPU propagates
the virtual register flags maintained in the target file itself. They are useful
to identify a certain type of machine operands while inserting spill stores and
reloads. Since RegAllocFast spills the physical register itself, there is no way
its virtual register can be mapped back to retrieve the flags. It can be solved
by passing the virtual register as an additional argument. This argument has no
use when the spill interfaces are called during the greedy allocator or even the
PrologEpilogInserter and can pass a null register in such cases.

Reviewed By: arsenm

Differential Revision: https://reviews.llvm.org/D138656
</pre>
</div>
</content>
</entry>
<entry>
<title>Use llvm::sort instead of std::sort where possible</title>
<updated>2022-07-23T13:19:05+00:00</updated>
<author>
<name>Dmitri Gribenko</name>
<email>gribozavr@gmail.com</email>
</author>
<published>2022-07-23T13:14:14+00:00</published>
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<id>aba43035bdf89c08409f0efccaf5408165abed9e</id>
<content type='text'>
llvm::sort is beneficial even when we use the iterator-based overload,
since it can optionally shuffle the elements (to detect
non-determinism). However llvm::sort is not usable everywhere, for
example, in compiler-rt.

Reviewed By: nhaehnle

Differential Revision: https://reviews.llvm.org/D130406
</content>
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<pre>
llvm::sort is beneficial even when we use the iterator-based overload,
since it can optionally shuffle the elements (to detect
non-determinism). However llvm::sort is not usable everywhere, for
example, in compiler-rt.

Reviewed By: nhaehnle

Differential Revision: https://reviews.llvm.org/D130406
</pre>
</div>
</content>
</entry>
<entry>
<title>[NFC] Use Register instead of unsigned</title>
<updated>2022-01-19T12:17:04+00:00</updated>
<author>
<name>Jim Lin</name>
<email>jim@andestech.com</email>
</author>
<published>2022-01-19T09:25:52+00:00</published>
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<id>d6b07348371247a2dff4635640af7be110bc7ee6</id>
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</content>
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<pre>
</pre>
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</content>
</entry>
<entry>
<title>[llvm] Use range-based for loops (NFC)</title>
<updated>2021-11-22T03:24:15+00:00</updated>
<author>
<name>Kazu Hirata</name>
<email>kazu@google.com</email>
</author>
<published>2021-11-22T03:24:15+00:00</published>
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<id>ea5421bd0db3e6782f60c53a7055eb11abed09c3</id>
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<pre>
</pre>
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