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<title>llvm-project.git/llvm/lib/Target/X86, branch users/nico/python-2</title>
<subtitle>Unnamed repository; edit this file 'description' to name the repository.
</subtitle>
<link rel='alternate' type='text/html' href='https://git.belthelziquor.com/llvm-project.git/'/>
<entry>
<title>[X86] commuteSelect - update to use SDPatternMatch. NFC. (#146868)</title>
<updated>2025-07-03T13:51:36+00:00</updated>
<author>
<name>Simon Pilgrim</name>
<email>llvm-dev@redking.me.uk</email>
</author>
<published>2025-07-03T13:51:36+00:00</published>
<link rel='alternate' type='text/html' href='https://git.belthelziquor.com/llvm-project.git/commit/?id=30eb97c5848d08eb0700a25359cc4926363a3fca'/>
<id>30eb97c5848d08eb0700a25359cc4926363a3fca</id>
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</content>
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<pre>
</pre>
</div>
</content>
</entry>
<entry>
<title>MCAsmBackend: Replace FKF_IsPCRel with isPCRel()</title>
<updated>2025-07-03T07:51:20+00:00</updated>
<author>
<name>Fangrui Song</name>
<email>i@maskray.me</email>
</author>
<published>2025-07-03T07:51:20+00:00</published>
<link rel='alternate' type='text/html' href='https://git.belthelziquor.com/llvm-project.git/commit/?id=b478c38c19f9e6ccc7ff2b6ede79a6e27ec20d19'/>
<id>b478c38c19f9e6ccc7ff2b6ede79a6e27ec20d19</id>
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<pre>
</pre>
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</entry>
<entry>
<title>MCAsmBackend: Simplify shouldForceRelocation overrides</title>
<updated>2025-07-03T06:30:36+00:00</updated>
<author>
<name>Fangrui Song</name>
<email>i@maskray.me</email>
</author>
<published>2025-07-03T06:30:36+00:00</published>
<link rel='alternate' type='text/html' href='https://git.belthelziquor.com/llvm-project.git/commit/?id=b59763a7db7fc502b4e1d8aaa4da319d85006066'/>
<id>b59763a7db7fc502b4e1d8aaa4da319d85006066</id>
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</content>
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<pre>
</pre>
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</content>
</entry>
<entry>
<title>MCAsmBackend: Merge addReloc into applyFixup (#146820)</title>
<updated>2025-07-03T06:14:11+00:00</updated>
<author>
<name>Fangrui Song</name>
<email>i@maskray.me</email>
</author>
<published>2025-07-03T06:14:11+00:00</published>
<link rel='alternate' type='text/html' href='https://git.belthelziquor.com/llvm-project.git/commit/?id=dd2891535d4b6d80f92d9a69e9db3b787203b9d0'/>
<id>dd2891535d4b6d80f92d9a69e9db3b787203b9d0</id>
<content type='text'>
Follow-up to #141333. Relocation generation called both addReloc and
applyFixup, with the default addReloc invoking shouldForceRelocation,
resulting in three virtual calls. This approach was also inflexible, as
targets needing additional data required extending
`shouldForceRelocation` (see #73721, resolved by #141311).

This change integrates relocation handling into applyFixup, eliminating
two virtual calls. The prior default addReloc is renamed to
maybeAddReloc. Targets overriding addReloc now call their customized
addReloc implementation.</content>
<content type='xhtml'>
<div xmlns='http://www.w3.org/1999/xhtml'>
<pre>
Follow-up to #141333. Relocation generation called both addReloc and
applyFixup, with the default addReloc invoking shouldForceRelocation,
resulting in three virtual calls. This approach was also inflexible, as
targets needing additional data required extending
`shouldForceRelocation` (see #73721, resolved by #141311).

This change integrates relocation handling into applyFixup, eliminating
two virtual calls. The prior default addReloc is renamed to
maybeAddReloc. Targets overriding addReloc now call their customized
addReloc implementation.</pre>
</div>
</content>
</entry>
<entry>
<title>[X86] Add BLEND/UNPCK shuffles to canCreateUndefOrPoisonForTargetNode/isGuaranteedNotToBeUndefOrPoisonForTargetNode (#146728)</title>
<updated>2025-07-02T17:38:00+00:00</updated>
<author>
<name>Simon Pilgrim</name>
<email>llvm-dev@redking.me.uk</email>
</author>
<published>2025-07-02T17:38:00+00:00</published>
<link rel='alternate' type='text/html' href='https://git.belthelziquor.com/llvm-project.git/commit/?id=aa8e1bc0e9892ddbd84333767f71dc191cc10140'/>
<id>aa8e1bc0e9892ddbd84333767f71dc191cc10140</id>
<content type='text'>
None of these implicitly generate UNDEF/POISON</content>
<content type='xhtml'>
<div xmlns='http://www.w3.org/1999/xhtml'>
<pre>
None of these implicitly generate UNDEF/POISON</pre>
</div>
</content>
</entry>
<entry>
<title>[DAG] Refactor X86 combineVSelectWithAllOnesOrZeros fold into a generic DAG Combine (#145298)</title>
<updated>2025-07-02T14:07:48+00:00</updated>
<author>
<name>woruyu</name>
<email>99597449+woruyu@users.noreply.github.com</email>
</author>
<published>2025-07-02T14:07:48+00:00</published>
<link rel='alternate' type='text/html' href='https://git.belthelziquor.com/llvm-project.git/commit/?id=bbcebec3af5ac473f5d3557683f18a79a4b12ab5'/>
<id>bbcebec3af5ac473f5d3557683f18a79a4b12ab5</id>
<content type='text'>
This PR resolves https://github.com/llvm/llvm-project/issues/144513

The modification include five pattern :
1.vselect Cond, 0, 0 → 0
2.vselect Cond, -1, 0 → bitcast Cond
3.vselect Cond, -1, x → or Cond, x
4.vselect Cond, x, 0 → and Cond, x
5.vselect Cond, 000..., X -&gt; andn Cond, X

1-4 have been migrated to DAGCombine. 5 still in x86 code.

The reason is that you cannot use the andn instruction directly in
DAGCombine, you can only use and+xor, which will introduce optimization
order issues. For example, in the x86 backend, select Cond, 0, x →
(~Cond) &amp; x, the backend will first check whether the cond node of
(~Cond) is a setcc node. If so, it will modify the comparison operator
of the condition.So the x86 backend cannot complete the optimization of
andn.In short, I think it is a better choice to keep the pattern of
vselect Cond, 000..., X instead of and+xor in combineDAG.

For commit, the first is code changes and x86 test(note 1), the second
is tests in other backend(node 2).

---------

Co-authored-by: Simon Pilgrim &lt;llvm-dev@redking.me.uk&gt;</content>
<content type='xhtml'>
<div xmlns='http://www.w3.org/1999/xhtml'>
<pre>
This PR resolves https://github.com/llvm/llvm-project/issues/144513

The modification include five pattern :
1.vselect Cond, 0, 0 → 0
2.vselect Cond, -1, 0 → bitcast Cond
3.vselect Cond, -1, x → or Cond, x
4.vselect Cond, x, 0 → and Cond, x
5.vselect Cond, 000..., X -&gt; andn Cond, X

1-4 have been migrated to DAGCombine. 5 still in x86 code.

The reason is that you cannot use the andn instruction directly in
DAGCombine, you can only use and+xor, which will introduce optimization
order issues. For example, in the x86 backend, select Cond, 0, x →
(~Cond) &amp; x, the backend will first check whether the cond node of
(~Cond) is a setcc node. If so, it will modify the comparison operator
of the condition.So the x86 backend cannot complete the optimization of
andn.In short, I think it is a better choice to keep the pattern of
vselect Cond, 000..., X instead of and+xor in combineDAG.

For commit, the first is code changes and x86 test(note 1), the second
is tests in other backend(node 2).

---------

Co-authored-by: Simon Pilgrim &lt;llvm-dev@redking.me.uk&gt;</pre>
</div>
</content>
</entry>
<entry>
<title>X86: Avoid some uses of getPointerTy (#146306)</title>
<updated>2025-07-02T13:14:16+00:00</updated>
<author>
<name>Matt Arsenault</name>
<email>Matthew.Arsenault@amd.com</email>
</author>
<published>2025-07-02T13:14:16+00:00</published>
<link rel='alternate' type='text/html' href='https://git.belthelziquor.com/llvm-project.git/commit/?id=dbe441e71611006c038254c12242a4fbc4d283ff'/>
<id>dbe441e71611006c038254c12242a4fbc4d283ff</id>
<content type='text'>
In most contexts the pointer type is implied by the operation
and should be propagated; getPointerTy is for niche cases where
there is a synthesized value.</content>
<content type='xhtml'>
<div xmlns='http://www.w3.org/1999/xhtml'>
<pre>
In most contexts the pointer type is implied by the operation
and should be propagated; getPointerTy is for niche cases where
there is a synthesized value.</pre>
</div>
</content>
</entry>
<entry>
<title>[X86] detectZextAbsDiff - use m_SpecificVectorElementVT matcher. NFC. (#146498)</title>
<updated>2025-07-01T10:59:37+00:00</updated>
<author>
<name>Simon Pilgrim</name>
<email>llvm-dev@redking.me.uk</email>
</author>
<published>2025-07-01T10:59:37+00:00</published>
<link rel='alternate' type='text/html' href='https://git.belthelziquor.com/llvm-project.git/commit/?id=fd46e409a91f66764b3c9d19dd3d6d3eb48c61ff'/>
<id>fd46e409a91f66764b3c9d19dd3d6d3eb48c61ff</id>
<content type='text'>
</content>
<content type='xhtml'>
<div xmlns='http://www.w3.org/1999/xhtml'>
<pre>
</pre>
</div>
</content>
</entry>
<entry>
<title>MC: Store fragment content and fixups out-of-line</title>
<updated>2025-07-01T07:21:12+00:00</updated>
<author>
<name>Fangrui Song</name>
<email>i@maskray.me</email>
</author>
<published>2025-07-01T07:21:12+00:00</published>
<link rel='alternate' type='text/html' href='https://git.belthelziquor.com/llvm-project.git/commit/?id=9beb467d9213fe2becdb0f1469d99ca058189ac7'/>
<id>9beb467d9213fe2becdb0f1469d99ca058189ac7</id>
<content type='text'>
Moved `Contents` and `Fixups` SmallVector storage to MCSection, enabling
trivial destructors for most fragment subclasses and eliminating the need
for MCFragment::destroy in ~MCSection.

For appending content to the current section, use
getContentsForAppending. During assembler relaxation, prefer
setContents/setFixups, which may involve copying and reduce the benefits
of https://reviews.llvm.org/D145791.

Moving only Contents out-of-line caused a slight performance regression
(Alexis Engelke's 2024 prototype). By also moving Fragments out-of-line,
fragment destructors become trivial, resulting in
neglgible instructions:u increase for "stage2-O0-g" and [large max-rss decrease](https://llvm-compile-time-tracker.com/compare.php?from=84e82746c3ff63ec23a8b85e9efd4f7fccf92590&amp;to=555a28c0b2f8250a9cf86fd267a04b0460283e15&amp;stat=max-rss&amp;linkStats=on)
for the "stage1-ReleaseLTO-g (link only)" benchmark.
(
An older version using fewer inline functions: https://llvm-compile-time-tracker.com/compare.php?from=bb982e733cfcda7e4cfb0583544f68af65211ed1&amp;to=f12d55f97c47717d438951ecddecf8ebd28c296b&amp;linkStats=on
)

Now using plain SmallVector in MCSection for storage, with potential for
future allocator optimizations, such as allocating `Contents` as the
trailing object of MCDataFragment. (GNU Assembler uses gnulib's obstack
for fragment management.)

Co-authored-by: Alexis Engelke &lt;engelke@in.tum.de&gt;

Pull Request: https://github.com/llvm/llvm-project/pull/146307
</content>
<content type='xhtml'>
<div xmlns='http://www.w3.org/1999/xhtml'>
<pre>
Moved `Contents` and `Fixups` SmallVector storage to MCSection, enabling
trivial destructors for most fragment subclasses and eliminating the need
for MCFragment::destroy in ~MCSection.

For appending content to the current section, use
getContentsForAppending. During assembler relaxation, prefer
setContents/setFixups, which may involve copying and reduce the benefits
of https://reviews.llvm.org/D145791.

Moving only Contents out-of-line caused a slight performance regression
(Alexis Engelke's 2024 prototype). By also moving Fragments out-of-line,
fragment destructors become trivial, resulting in
neglgible instructions:u increase for "stage2-O0-g" and [large max-rss decrease](https://llvm-compile-time-tracker.com/compare.php?from=84e82746c3ff63ec23a8b85e9efd4f7fccf92590&amp;to=555a28c0b2f8250a9cf86fd267a04b0460283e15&amp;stat=max-rss&amp;linkStats=on)
for the "stage1-ReleaseLTO-g (link only)" benchmark.
(
An older version using fewer inline functions: https://llvm-compile-time-tracker.com/compare.php?from=bb982e733cfcda7e4cfb0583544f68af65211ed1&amp;to=f12d55f97c47717d438951ecddecf8ebd28c296b&amp;linkStats=on
)

Now using plain SmallVector in MCSection for storage, with potential for
future allocator optimizations, such as allocating `Contents` as the
trailing object of MCDataFragment. (GNU Assembler uses gnulib's obstack
for fragment management.)

Co-authored-by: Alexis Engelke &lt;engelke@in.tum.de&gt;

Pull Request: https://github.com/llvm/llvm-project/pull/146307
</pre>
</div>
</content>
</entry>
<entry>
<title>[X86][llvm-exegesis] fix LNLP performance counter binding issue (#146348)</title>
<updated>2025-07-01T04:59:23+00:00</updated>
<author>
<name>Mahesh-Attarde</name>
<email>mahesh.attarde@intel.com</email>
</author>
<published>2025-07-01T04:59:23+00:00</published>
<link rel='alternate' type='text/html' href='https://git.belthelziquor.com/llvm-project.git/commit/?id=84e82746c3ff63ec23a8b85e9efd4f7fccf92590'/>
<id>84e82746c3ff63ec23a8b85e9efd4f7fccf92590</id>
<content type='text'>
We added LNLP sched model recently, PFM counter bounding names needs to
match cpu string.
llvm-exegesis wont produce results without correct naming.

Co-authored-by: mattarde &lt;mattarde@intel.com&gt;</content>
<content type='xhtml'>
<div xmlns='http://www.w3.org/1999/xhtml'>
<pre>
We added LNLP sched model recently, PFM counter bounding names needs to
match cpu string.
llvm-exegesis wont produce results without correct naming.

Co-authored-by: mattarde &lt;mattarde@intel.com&gt;</pre>
</div>
</content>
</entry>
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