llvm-project.git/llvm/lib/Target/X86/X86TargetMachine.cpp, branch users/koachan/spr/main.sparcias-enable-parseforallfeatures-in-matchoperandparserimpl

[X86] Add AMXProgModel to YAML serialization (#94988)

2024-06-11T11:08:55+00:00

This allows tested passes to depend on the AMX model in the function
info. Preparatory work for to adopt #94358 for other AMX passes.

Reland "[NewPM][CodeGen] Port selection dag isel to new pass manager" (#94149)

2024-06-04T00:10:58+00:00

- Fix build with `EXPENSIVE_CHECKS`
- Remove unused `PassName::ID` to resolve warning
- Mark `~SelectionDAGISel` virtual so AArch64 backend can work properly

Revert "[NewPM][CodeGen] Port selection dag isel to new pass manager" (#94146)

2024-06-02T06:31:52+00:00

This reverts commit de37c06f01772e02465ccc9f538894c76d89a7a1 to
de37c06f01772e02465ccc9f538894c76d89a7a1

It still breaks EXPENSIVE_CHECKS build. Sorry.

[NewPM][CodeGen] Port selection dag isel to new pass manager (#83567)

2024-06-02T01:12:33+00:00

Port selection dag isel to new pass manager.
Only `AMDGPU` and `X86` support new pass version. `-verify-machineinstrs` in new pass manager belongs to verify instrumentation, it is enabled by default.

[X86][GlobalISel] Enable G_BUILD_VECTOR and G_CONSTANT_POOL (#92844)

2024-05-29T22:53:43+00:00

* Add support for G_LOAD from G_CONSTANT_POOL on X86 and X64
* Add X86GlobalBaseRegPass to handle base register initialization for
X86.
* Fix vector type legalization for G_STORE and G_LOAD as well as enable
scalarization for them.
* Custom lower G_BUILD_VECTOR into G_LOAD from G_CONSTANT_POOL.

[X86] getEffectiveX86CodeModel - take a Triple argument instead of just a Is64Bit flag. NFC. (#87479)

2024-04-03T14:06:54+00:00

Matches what most other targets do and makes it easier to specify code model based off other triple settings in the future.

[CodeGen] Port AtomicExpand to new Pass Manager (#71220)

2024-02-25T13:12:22+00:00

Port the `atomicexpand` pass to the new Pass Manager. 
Fixes #64559

[X86] Add missing pass initialization calls. (#82447)

2024-02-21T05:11:01+00:00

If the passes aren't registered, they don't show up in print-after-all.

[X86] Fix RTTI proxy emission for 32-bit (#78622)

2024-01-18T21:31:33+00:00

32-bit x86 doesn't have an appropriate relocation type we can use to
elide the RTTI proxies, so we need to emit them. This would previously
cause crashes when using the relative vtable ABI for 32-bit x86.

[X86][NFC] Rename variables/passes for EVEX compression optimization

2024-01-06T04:41:09+00:00

RFC: https://discourse.llvm.org/t/rfc-design-for-apx-feature-egpr-and-ndd-support/73031

APX introduces EGPR, NDD and NF instructions. In addition to compressing
EVEX encoded AVX512 instructions into VEX encoding, we also have several
more possible optimizations.

a. Promoted instruction (EVEX space) -> pre-promotion instruction (legacy space)
b. NDD (EVEX space) -> non-NDD (legacy space)
c. NF_ND (EVEX space) -> NF (EVEX space)

The first two types of compression can usually reduce code size, while
the third type of compression can help hardware decode although the
instruction length remains unchanged.

So we do the renaming for the upcoming APX optimizations.

BTW, I clang-format the code in X86CompressEVEX.cpp,
X86CompressEVEXTablesEmitter.cpp.

This patch also extracts the NFC in #77065 into a separate commit.