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<title>llvm-project.git/llvm/lib/Target/X86/X86Subtarget.cpp, branch main</title>
<subtitle>Unnamed repository; edit this file 'description' to name the repository.
</subtitle>
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<entry>
<title>Cleanups in AArch64 (#168025)</title>
<updated>2025-11-15T19:55:39+00:00</updated>
<author>
<name>Eric Christopher</name>
<email>echristo@gmail.com</email>
</author>
<published>2025-11-15T19:55:39+00:00</published>
<link rel='alternate' type='text/html' href='https://git.belthelziquor.com/llvm-project.git/commit/?id=95c93f40ac186be1e16e5b6216b98f9addbe3806'/>
<id>95c93f40ac186be1e16e5b6216b98f9addbe3806</id>
<content type='text'>
Forward declare a couple of classes for simplicity, remove some unused
headers, clean up a comment.

Tested with check-all.</content>
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<pre>
Forward declare a couple of classes for simplicity, remove some unused
headers, clean up a comment.

Tested with check-all.</pre>
</div>
</content>
</entry>
<entry>
<title>Default stack alignment of X86 Hurd to 16 bytes (#158454)</title>
<updated>2025-09-22T07:11:54+00:00</updated>
<author>
<name>Brad Smith</name>
<email>brad@comstyle.com</email>
</author>
<published>2025-09-22T07:11:54+00:00</published>
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<id>8323ff0c59739e4735fd896fad4be05e54432815</id>
<content type='text'>
https://sourceware.org/bugzilla/show_bug.cgi?id=21120</content>
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<pre>
https://sourceware.org/bugzilla/show_bug.cgi?id=21120</pre>
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</content>
</entry>
<entry>
<title>[X86][AVX10] Remove EVEX512 and AVX10-256 implementations (#157034)</title>
<updated>2025-09-05T14:08:59+00:00</updated>
<author>
<name>Phoebe Wang</name>
<email>phoebe.wang@intel.com</email>
</author>
<published>2025-09-05T14:08:59+00:00</published>
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<id>94b164c21814ab74201aba39e060f3a876fcb335</id>
<content type='text'>
The 256-bit maximum vector register size control was removed from AVX10
whitepaper, ref: https://cdrdv2.intel.com/v1/dl/getContent/784343

We have warned these options in LLVM21 through #132542. This patch
removes underlying implementations in LLVM22.</content>
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<pre>
The 256-bit maximum vector register size control was removed from AVX10
whitepaper, ref: https://cdrdv2.intel.com/v1/dl/getContent/784343

We have warned these options in LLVM21 through #132542. This patch
removes underlying implementations in LLVM22.</pre>
</div>
</content>
</entry>
<entry>
<title>[X86] Use array instead of SmallVector. NFC (#155321)</title>
<updated>2025-08-26T16:09:48+00:00</updated>
<author>
<name>Craig Topper</name>
<email>craig.topper@sifive.com</email>
</author>
<published>2025-08-26T16:09:48+00:00</published>
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<id>fbd2f479474a5d071f234e9349f9543c235c0d25</id>
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</content>
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<pre>
</pre>
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</content>
</entry>
<entry>
<title>Remove Native Client support (#133661)</title>
<updated>2025-07-15T17:22:33+00:00</updated>
<author>
<name>Brad Smith</name>
<email>brad@comstyle.com</email>
</author>
<published>2025-07-15T17:22:33+00:00</published>
<link rel='alternate' type='text/html' href='https://git.belthelziquor.com/llvm-project.git/commit/?id=0d2e11f3e834e0c1803a6e00da35525b0d476eb2'/>
<id>0d2e11f3e834e0c1803a6e00da35525b0d476eb2</id>
<content type='text'>
Remove the Native Client support now that it has finally reached end of life.</content>
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<pre>
Remove the Native Client support now that it has finally reached end of life.</pre>
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</content>
</entry>
<entry>
<title>Mips/X86: Use reportFatalUsageError for subtarget construction errors (#142028)</title>
<updated>2025-05-30T06:03:50+00:00</updated>
<author>
<name>Matt Arsenault</name>
<email>Matthew.Arsenault@amd.com</email>
</author>
<published>2025-05-30T06:03:50+00:00</published>
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<id>72a3c7610b4f97b43d5cd30f1d5b95bad5e77640</id>
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</content>
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<pre>
</pre>
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</entry>
<entry>
<title>[CodeGen] Prune headers and move code out of line for build efficiency, NFC (#135622)</title>
<updated>2025-04-15T05:23:18+00:00</updated>
<author>
<name>Reid Kleckner</name>
<email>rnk@google.com</email>
</author>
<published>2025-04-15T05:23:18+00:00</published>
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<id>2538c607e903a1fe0cfcacd5732235cc8ff3adf7</id>
<content type='text'>
I noticed these destructors taking time with -ftime-trace and moved some
of them for minor build efficiency improvements.

The main impact of moving destructors out of line is that it avoids
requiring container fields containing other types from being complete,
i.e. one can have uptr&lt;T&gt; or vector&lt;T&gt; as a field with an incomplete
type T, and that means we can reduce transitive includes, as with
LegalizerInfo.h.

Move expensive getDebugOperandsForReg template out-of-line. The
std::function instantiation shows up in time trace even if you don't use
the function.</content>
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<pre>
I noticed these destructors taking time with -ftime-trace and moved some
of them for minor build efficiency improvements.

The main impact of moving destructors out of line is that it avoids
requiring container fields containing other types from being complete,
i.e. one can have uptr&lt;T&gt; or vector&lt;T&gt; as a field with an incomplete
type T, and that means we can reduce transitive includes, as with
LegalizerInfo.h.

Move expensive getDebugOperandsForReg template out-of-line. The
std::function instantiation shows up in time trace even if you don't use
the function.</pre>
</div>
</content>
</entry>
<entry>
<title>[X86] Use a range-based for loop (NFC) (#103519)</title>
<updated>2024-08-14T04:56:11+00:00</updated>
<author>
<name>Kazu Hirata</name>
<email>kazu@google.com</email>
</author>
<published>2024-08-14T04:56:11+00:00</published>
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<id>e8f312de78577e14154c10db0cb71147c182b69a</id>
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</content>
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<pre>
</pre>
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</content>
</entry>
<entry>
<title>[Driver,CodeGen] Report error when enabling 64-bit-only features on non-64-bit arch (#101151)</title>
<updated>2024-07-31T02:38:33+00:00</updated>
<author>
<name>Shengchen Kan</name>
<email>shengchen.kan@intel.com</email>
</author>
<published>2024-07-31T02:38:33+00:00</published>
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<id>fd6faee5b3b5a7c0e5e87aa0b5719a1a48159ea0</id>
<content type='text'>
In front-end, now we detect for `-mapx-features=/-mapxf` and `-muintr`,
which is aligned with GCC

https://gcc.gnu.org/bugzilla/attachment.cgi?id=58698&amp;action=diff

In backend, we just disable these 64-bit-only features silently, so that
there is no error for
`-march=native -m32` on APX-supported arch.

llvm-issue: https://github.com/llvm/llvm-project/issues/94810
GCC thread: https://gcc.gnu.org/bugzilla/show_bug.cgi?id=115978</content>
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<pre>
In front-end, now we detect for `-mapx-features=/-mapxf` and `-muintr`,
which is aligned with GCC

https://gcc.gnu.org/bugzilla/attachment.cgi?id=58698&amp;action=diff

In backend, we just disable these 64-bit-only features silently, so that
there is no error for
`-march=native -m32` on APX-supported arch.

llvm-issue: https://github.com/llvm/llvm-project/issues/94810
GCC thread: https://gcc.gnu.org/bugzilla/show_bug.cgi?id=115978</pre>
</div>
</content>
</entry>
<entry>
<title>Remove support for 3DNow!, both intrinsics and builtins. (#96246)</title>
<updated>2024-07-16T16:08:48+00:00</updated>
<author>
<name>James Y Knight</name>
<email>jyknight@google.com</email>
</author>
<published>2024-07-16T16:08:48+00:00</published>
<link rel='alternate' type='text/html' href='https://git.belthelziquor.com/llvm-project.git/commit/?id=f0eb5587ceeb641445b64cb264c822b4751de04a'/>
<id>f0eb5587ceeb641445b64cb264c822b4751de04a</id>
<content type='text'>
This set of instructions was only supported by AMD chips starting in
the K6-2 (introduced 1998), and before the "Bulldozer" family
(2011). They were never much used, as they were effectively superseded
by the more-widely-implemented SSE (first implemented on the AMD side
in Athlon XP in 2001).

This is being done as a predecessor towards general removal of MMX
register usage. Since there is almost no usage of the 3DNow!
intrinsics, and no modern hardware even implements them, simple
removal seems like the best option.

(Clang half originally uploaded in https://reviews.llvm.org/D94213)

Works towards issue #41665 and issue #98272.</content>
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<pre>
This set of instructions was only supported by AMD chips starting in
the K6-2 (introduced 1998), and before the "Bulldozer" family
(2011). They were never much used, as they were effectively superseded
by the more-widely-implemented SSE (first implemented on the AMD side
in Athlon XP in 2001).

This is being done as a predecessor towards general removal of MMX
register usage. Since there is almost no usage of the 3DNow!
intrinsics, and no modern hardware even implements them, simple
removal seems like the best option.

(Clang half originally uploaded in https://reviews.llvm.org/D94213)

Works towards issue #41665 and issue #98272.</pre>
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</entry>
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