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<title>llvm-project.git/llvm/lib/Target/X86/X86InstrSystem.td, branch main</title>
<subtitle>Unnamed repository; edit this file 'description' to name the repository.
</subtitle>
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<entry>
<title>[TableGen][SelectionDAG] Remove the `implicit` DAG node (#115295)</title>
<updated>2024-11-09T04:25:40+00:00</updated>
<author>
<name>Sergei Barannikov</name>
<email>barannikov88@gmail.com</email>
</author>
<published>2024-11-09T04:25:40+00:00</published>
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<id>501a58344179242f702f55e0ee5c039290426c54</id>
<content type='text'>
The node was introduced in 59c39dc1 and was intended to allow writing
patterns like this:
`[(set AL, (mul AL, GR8:$src1)), (implicit EFLAGS)]`

However, it does not introduce new functionality because the same
pattern can be equivalently expressed as:
`[(set AL, EFLAGS, (mul AL, GR8:$src1))]`

The latter form is also more flexible as it allows reordering output
operands.

In most places uses of `implicit` were redundant -- removing them didn't
change anything in the generated DAG tables. The only three cases where
it did have effect are in X86InstrArithmetic.td and X86InstrSystem.td --
those were rewritten to use `set` node.

Removing `implicit` from some patterns made them importable by GISel,
hence the change in a test.</content>
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<pre>
The node was introduced in 59c39dc1 and was intended to allow writing
patterns like this:
`[(set AL, (mul AL, GR8:$src1)), (implicit EFLAGS)]`

However, it does not introduce new functionality because the same
pattern can be equivalently expressed as:
`[(set AL, EFLAGS, (mul AL, GR8:$src1))]`

The latter form is also more flexible as it allows reordering output
operands.

In most places uses of `implicit` were redundant -- removing them didn't
change anything in the generated DAG tables. The only three cases where
it did have effect are in X86InstrArithmetic.td and X86InstrSystem.td --
those were rewritten to use `set` node.

Removing `implicit` from some patterns made them importable by GISel,
hence the change in a test.</pre>
</div>
</content>
</entry>
<entry>
<title>[X86][MC] Support instructions of MSR_IMM (#113524)</title>
<updated>2024-10-28T04:59:51+00:00</updated>
<author>
<name>Freddy Ye</name>
<email>freddy.ye@intel.com</email>
</author>
<published>2024-10-28T04:59:51+00:00</published>
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<id>d3f70db51cbc0876937d404e96fbda04df793bd4</id>
<content type='text'>
Ref.: https://cdrdv2.intel.com/v1/dl/getContent/671368</content>
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<pre>
Ref.: https://cdrdv2.intel.com/v1/dl/getContent/671368</pre>
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</content>
</entry>
<entry>
<title>[X86][MC] Support Intel FRED and LKGS instructions. (#91909)</title>
<updated>2024-05-15T02:40:16+00:00</updated>
<author>
<name>Freddy Ye</name>
<email>freddy.ye@intel.com</email>
</author>
<published>2024-05-15T02:40:16+00:00</published>
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<id>13b265c7b5c6a989427639e33893c158f737480b</id>
<content type='text'>
Spec reference: https://cdrdv2.intel.com/v1/dl/getContent/678938</content>
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<pre>
Spec reference: https://cdrdv2.intel.com/v1/dl/getContent/678938</pre>
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</content>
</entry>
<entry>
<title>[X86][MC] Teach disassembler to recognize apx instructions which ignores W bit (#82747)</title>
<updated>2024-02-29T03:44:41+00:00</updated>
<author>
<name>XinWang10</name>
<email>108658776+XinWang10@users.noreply.github.com</email>
</author>
<published>2024-02-29T03:44:41+00:00</published>
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<id>ffa48f0c945be3c1680b0830d5c0cac146cb954c</id>
<content type='text'>
Extended VMX instructions and 8 bit apx extended instructions don't need
W bit, they are marked as W ignored in spec.
RFC:
https://discourse.llvm.org/t/rfc-design-for-apx-feature-egpr-and-ndd-support/73031/4</content>
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<pre>
Extended VMX instructions and 8 bit apx extended instructions don't need
W bit, they are marked as W ignored in spec.
RFC:
https://discourse.llvm.org/t/rfc-design-for-apx-feature-egpr-and-ndd-support/73031/4</pre>
</div>
</content>
</entry>
<entry>
<title>[LLVM][X86] Add EFLAGS Defs for VERR/VERW instructions (#81824)</title>
<updated>2024-02-15T06:04:53+00:00</updated>
<author>
<name>riChar</name>
<email>wxsychi@163.com</email>
</author>
<published>2024-02-15T06:04:53+00:00</published>
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<id>94f51649c4a574f88fd9b8a2d0a05b334c0bd490</id>
<content type='text'>
VERR/VERW instructions will define ZF flag.</content>
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<pre>
VERR/VERW instructions will define ZF flag.</pre>
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</content>
</entry>
<entry>
<title>[clang][X86] X86::LAR X86::LSL add_implicate eflags (#80993)</title>
<updated>2024-02-15T04:53:56+00:00</updated>
<author>
<name>Qfrost</name>
<email>root@qfrost.com</email>
</author>
<published>2024-02-15T04:53:56+00:00</published>
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<id>bfe302c58321abd79a5db7e805ef4b4db24df820</id>
<content type='text'>
[@xia0ji233](https://github.com/xia0ji233) and I found that X86::LAR and
X86::lSR implicit use eflags register. However, it was not been defined
in LLVM, which means we will get wrong alive-result if we use these two
instructions.
![T~
_81W6A}J}{AP{DF%E}KY](https://github.com/llvm/llvm-project/assets/58380176/b84e758b-2978-49e7-a11c-726fd66e1976)</content>
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<pre>
[@xia0ji233](https://github.com/xia0ji233) and I found that X86::LAR and
X86::lSR implicit use eflags register. However, it was not been defined
in LLVM, which means we will get wrong alive-result if we use these two
instructions.
![T~
_81W6A}J}{AP{DF%E}KY](https://github.com/llvm/llvm-project/assets/58380176/b84e758b-2978-49e7-a11c-726fd66e1976)</pre>
</div>
</content>
</entry>
<entry>
<title>[X86] Support promoted ENQCMD, KEYLOCKER and USERMSR (#77293)</title>
<updated>2024-01-26T06:24:43+00:00</updated>
<author>
<name>XinWang10</name>
<email>108658776+XinWang10@users.noreply.github.com</email>
</author>
<published>2024-01-26T06:24:43+00:00</published>
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<id>6d0080b5de26d8a8682ec6169851af3d04e30ccb</id>
<content type='text'>
R16-R31 was added into GPRs in
https://github.com/llvm/llvm-project/pull/70958,
This patch supports the promoted ENQCMD, KEYLOCKER and USER-MSR
instructions in EVEX space.

RFC:
https://discourse.llvm.org/t/rfc-design-for-apx-feature-egpr-and-ndd-support/73031/4</content>
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<pre>
R16-R31 was added into GPRs in
https://github.com/llvm/llvm-project/pull/70958,
This patch supports the promoted ENQCMD, KEYLOCKER and USER-MSR
instructions in EVEX space.

RFC:
https://discourse.llvm.org/t/rfc-design-for-apx-feature-egpr-and-ndd-support/73031/4</pre>
</div>
</content>
</entry>
<entry>
<title>[X86]Support lowering for APX Promoted SHA/MOVDIR/CRC32/INVPCID/CET instructions (#76786)</title>
<updated>2024-01-05T07:56:15+00:00</updated>
<author>
<name>XinWang10</name>
<email>108658776+XinWang10@users.noreply.github.com</email>
</author>
<published>2024-01-05T07:56:15+00:00</published>
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<id>f5f66e26b5f010218651cab831d5651fe7a71a0a</id>
<content type='text'>
R16-R31 was added into GPRs in
https://github.com/llvm/llvm-project/pull/70958,
This patch supports the lowering for promoted
SHA/MOVDIR/CRC32/INVPCID/CET.

RFC:
https://discourse.llvm.org/t/rfc-design-for-apx-feature-egpr-and-ndd-support/73031/4</content>
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<div xmlns='http://www.w3.org/1999/xhtml'>
<pre>
R16-R31 was added into GPRs in
https://github.com/llvm/llvm-project/pull/70958,
This patch supports the lowering for promoted
SHA/MOVDIR/CRC32/INVPCID/CET.

RFC:
https://discourse.llvm.org/t/rfc-design-for-apx-feature-egpr-and-ndd-support/73031/4</pre>
</div>
</content>
</entry>
<entry>
<title>[X86] Correct operand order of UWRMSR. (#76389)</title>
<updated>2023-12-27T01:01:55+00:00</updated>
<author>
<name>Freddy Ye</name>
<email>freddy.ye@intel.com</email>
</author>
<published>2023-12-27T01:01:55+00:00</published>
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<id>8ddb0fcff9ec73aeef20b1288b4ab5e03cd0bd56</id>
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</content>
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<pre>
</pre>
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</content>
</entry>
<entry>
<title>[X86][NFC] Set default OpPrefix to PS for XOP/VEX/EVEX instructions</title>
<updated>2023-12-24T02:20:40+00:00</updated>
<author>
<name>Shengchen Kan</name>
<email>shengchen.kan@intel.com</email>
</author>
<published>2023-12-23T13:41:53+00:00</published>
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<id>6e20df1a3b0f7654b2821fe182c7ae9bd52672e6</id>
<content type='text'>
It helps simplify the class definitions. Now, the only explicit usage of PS is
to check prefix 0x66/0xf2/0xf3 can not be used a prefix, e.g. wbinvd.

See 82974e0114f02ffc07557e217d87f8dc4e100a26 for more details.
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<pre>
It helps simplify the class definitions. Now, the only explicit usage of PS is
to check prefix 0x66/0xf2/0xf3 can not be used a prefix, e.g. wbinvd.

See 82974e0114f02ffc07557e217d87f8dc4e100a26 for more details.
</pre>
</div>
</content>
</entry>
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