This will make it possible for tablegen to make subtarget
dependent decisions without adding new arguments to every
target.

---------

Co-authored-by: Sergei Barannikov <barannikov88@gmail.com>

The goal is to remove redundant TEST*ri instructions, especially with NF
feature. Other tests are side effects due to longer live range of
EFLAGS. https://godbolt.org/z/PbaTj1oa3

Reland with fix to buildbot failures.

Reverts llvm/llvm-project#155586

Breaks bots, see details in #155586.

The goal is to remove redundant TEST*ri instructions, especially with NF
feature. Other tests are side effects due to longer live range of
EFLAGS. https://godbolt.org/z/PbaTj1oa3

When avx512fp16 is not available, we use MOVSS to spill fr16/fr16x
register.
However The MOVSSmr require fr32 register class and MOVSSrm require
vr128
register class which cause bad instruction detected by machine verifier.
To fix the issue this patch is to create a pseudo instruction MOVSHP for
fr16 register spilling. MOVSHP is expanded to MOVSS or VMOVSSZ depending
on the register number.

---------

Co-authored-by: Yuanke Luo <ykluo@birentech.com>

This reverts commit 518703806286c98bac7b84156738839f8bd55bef.

Failing M68k build bot.

All these platforms defined their predicate in such a way to allow bit
twiddling to get inverse predicates

Just commute with (V)BLENDPD/S like all other BLEND instructions

This is now handled more generally by the X86FixupInstTuningPass (OptSize fold occurs even without a scheduler model).

First step towards #142972

Noticed while preparing for #142972

This is the x64 equivalent of #121516

Since import call optimization was originally [added to x64 Windows to
implement a more efficient retpoline
mitigation](https://techcommunity.microsoft.com/blog/windowsosplatform/mitigating-spectre-variant-2-with-retpoline-on-windows/295618)
the section and constant names relating to this all mention "retpoline"
and we need to mark indirect calls, control-flow guard calls and jumps
for jump tables in the section alongside calls to imported functions.

As with the AArch64 feature, this emits a new section into the obj which
is used by the MSVC linker to generate the Dynamic Value Relocation
Table and the section itself does not appear in the final binary.

The Windows Loader requires a specific sequence of instructions be
emitted when this feature is enabled:
* Indirect calls/jumps must have the function pointer to jump to in
`rax`.
* Calls to imported functions must use the `rex` prefix and be followed
by a 5-byte nop.
* Indirect calls must be followed by a 3-byte nop.