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<title>llvm-project.git/llvm/lib/Target/X86/X86DomainReassignment.cpp, branch users/nico/python-2</title>
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<entry>
<title>[X86] Use Register and MCRegister. NFC</title>
<updated>2025-03-16T06:15:28+00:00</updated>
<author>
<name>Craig Topper</name>
<email>craig.topper@sifive.com</email>
</author>
<published>2025-03-15T17:33:19+00:00</published>
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<entry>
<title>[X86] Avoid repeated hash lookups (NFC) (#126857)</title>
<updated>2025-02-12T15:38:01+00:00</updated>
<author>
<name>Kazu Hirata</name>
<email>kazu@google.com</email>
</author>
<published>2025-02-12T15:38:01+00:00</published>
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<pre>
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<entry>
<title>[X86] Remove unused includes (NFC) (#115593)</title>
<updated>2024-11-09T16:23:46+00:00</updated>
<author>
<name>Kazu Hirata</name>
<email>kazu@google.com</email>
</author>
<published>2024-11-09T16:23:46+00:00</published>
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Identified with misc-include-cleaner.</content>
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<pre>
Identified with misc-include-cleaner.</pre>
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</entry>
<entry>
<title>[X86] Speed up X86 Domain Reassignment pass by early return (#108108)</title>
<updated>2024-09-18T16:12:04+00:00</updated>
<author>
<name>weiguozhi</name>
<email>57237827+weiguozhi@users.noreply.github.com</email>
</author>
<published>2024-09-18T16:12:04+00:00</published>
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Current implementation of X86 Domain Reassignment pass is finding out
the complete closure of a general register, then check if it's possible
to change the domain. It causes compile time issue when compiling large
functions. This patch checks the possibility of change domain in the
process of constructing closure, if it's illegal to change domain, we
can return immedietely.

For one of our large files, it reduced X86 Domain Reassignment pass time
from 200+ seconds to less than 1s.</content>
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<pre>
Current implementation of X86 Domain Reassignment pass is finding out
the complete closure of a general register, then check if it's possible
to change the domain. It causes compile time issue when compiling large
functions. This patch checks the possibility of change domain in the
process of constructing closure, if it's illegal to change domain, we
can return immedietely.

For one of our large files, it reduced X86 Domain Reassignment pass time
from 200+ seconds to less than 1s.</pre>
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</content>
</entry>
<entry>
<title>[X86] Consistently use 'k' for predicate mask registers in instruction names (#108780)</title>
<updated>2024-09-17T07:57:57+00:00</updated>
<author>
<name>Simon Pilgrim</name>
<email>llvm-dev@redking.me.uk</email>
</author>
<published>2024-09-17T07:57:57+00:00</published>
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<id>c91f2a259f378a9a4817c675b9a01557fcf7cae8</id>
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We use 'k' for move instructions and to indicate masked variants of evex instructions, but otherwise we're very inconsistent when we use 'k' vs 'r'.</content>
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<pre>
We use 'k' for move instructions and to indicate masked variants of evex instructions, but otherwise we're very inconsistent when we use 'k' vs 'r'.</pre>
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</entry>
<entry>
<title>[X86][RA] Add two address hints for compressible NDD instructions. (#98603)</title>
<updated>2024-08-06T00:52:48+00:00</updated>
<author>
<name>Freddy Ye</name>
<email>freddy.ye@intel.com</email>
</author>
<published>2024-08-06T00:52:48+00:00</published>
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<content type='text'>
To address @topperc 's comment at
https://discourse.llvm.org/t/rfc-design-for-apx-feature-egpr-and-ndd-support/73031/5?u=kanrobert</content>
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<pre>
To address @topperc 's comment at
https://discourse.llvm.org/t/rfc-design-for-apx-feature-egpr-and-ndd-support/73031/5?u=kanrobert</pre>
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</entry>
<entry>
<title>[X86] Support DomainReassignment for APX NDD instructions (#85737)</title>
<updated>2024-03-22T00:52:40+00:00</updated>
<author>
<name>Freddy Ye</name>
<email>freddy.ye@intel.com</email>
</author>
<published>2024-03-22T00:52:40+00:00</published>
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<entry>
<title>[X86] Skip unused VRegs traverse (#78229)</title>
<updated>2024-01-26T22:57:14+00:00</updated>
<author>
<name>Evgenii Kudriashov</name>
<email>evgenii.kudriashov@intel.com</email>
</author>
<published>2024-01-26T22:57:14+00:00</published>
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<id>cfd91199caed12b3f40ab35cf7f6c7fbce38d776</id>
<content type='text'>
Almost all loops with getNumVirtRegs skip unused registers by means
of reg_nodbg_empty or empty live interval. Except for these two cases
that are revealed by GlobalISel since it can skip RegClass assignment
for unused registers.

Closes #64452, closes #71926</content>
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<pre>
Almost all loops with getNumVirtRegs skip unused registers by means
of reg_nodbg_empty or empty live interval. Except for these two cases
that are revealed by GlobalISel since it can skip RegClass assignment
for unused registers.

Closes #64452, closes #71926</pre>
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</entry>
<entry>
<title>[X86]Support lowering for APX Promoted SHA/MOVDIR/CRC32/INVPCID/CET instructions (#76786)</title>
<updated>2024-01-05T07:56:15+00:00</updated>
<author>
<name>XinWang10</name>
<email>108658776+XinWang10@users.noreply.github.com</email>
</author>
<published>2024-01-05T07:56:15+00:00</published>
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<content type='text'>
R16-R31 was added into GPRs in
https://github.com/llvm/llvm-project/pull/70958,
This patch supports the lowering for promoted
SHA/MOVDIR/CRC32/INVPCID/CET.

RFC:
https://discourse.llvm.org/t/rfc-design-for-apx-feature-egpr-and-ndd-support/73031/4</content>
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<pre>
R16-R31 was added into GPRs in
https://github.com/llvm/llvm-project/pull/70958,
This patch supports the lowering for promoted
SHA/MOVDIR/CRC32/INVPCID/CET.

RFC:
https://discourse.llvm.org/t/rfc-design-for-apx-feature-egpr-and-ndd-support/73031/4</pre>
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</entry>
<entry>
<title>[X86][CodeGen] Prefer KMOVkk_EVEX than KMOVkk when EGPR is supported (#74048)</title>
<updated>2023-12-02T14:43:02+00:00</updated>
<author>
<name>Shengchen Kan</name>
<email>shengchen.kan@intel.com</email>
</author>
<published>2023-12-02T14:43:02+00:00</published>
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<content type='text'>
In memory fold table, we have

```
 {X86::KMOVDkk, X86::KMOVDkm, 0},
 {X86::KMOVDkk_EVEX, X86::KMOVDkm_EVEX, 0}
```

where `KMOVDkm_EVEX` can use EGPR as base and index registers, while
`KMOVDkm` can't. Hence, though `KMOVkk` does not have any GPR operands,
we prefer to use `KMOVDkk_EVEX` to help register allocation.

It will be compressed to `KMOVDkk` in EVEX2VEX pass if memory folding
does not happen.</content>
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<pre>
In memory fold table, we have

```
 {X86::KMOVDkk, X86::KMOVDkm, 0},
 {X86::KMOVDkk_EVEX, X86::KMOVDkm_EVEX, 0}
```

where `KMOVDkm_EVEX` can use EGPR as base and index registers, while
`KMOVDkm` can't. Hence, though `KMOVkk` does not have any GPR operands,
we prefer to use `KMOVDkk_EVEX` to help register allocation.

It will be compressed to `KMOVDkk` in EVEX2VEX pass if memory folding
does not happen.</pre>
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