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<title>llvm-project.git/llvm/lib/Target/X86/Disassembler/X86Disassembler.cpp, branch users/nico/python-2</title>
<subtitle>Unnamed repository; edit this file 'description' to name the repository.
</subtitle>
<link rel='alternate' type='text/html' href='https://git.belthelziquor.com/llvm-project.git/'/>
<entry>
<title>Revert "[X86][AVX10.2] Support YMM rounding new instructions (#101825)" (#132362)</title>
<updated>2025-03-21T12:12:57+00:00</updated>
<author>
<name>Phoebe Wang</name>
<email>phoebe.wang@intel.com</email>
</author>
<published>2025-03-21T12:12:57+00:00</published>
<link rel='alternate' type='text/html' href='https://git.belthelziquor.com/llvm-project.git/commit/?id=09feaa9261448e72ce21394613e0a12f84c1b8d9'/>
<id>09feaa9261448e72ce21394613e0a12f84c1b8d9</id>
<content type='text'>
This reverts commit 0dba5381d8c8e4cadc32a067bf2fe5e3486ae53d.

YMM rounding was removed from AVX10 whitepaper. Ref:
https://cdrdv2.intel.com/v1/dl/getContent/784343

The MINMAX and SATURATING CONVERT instructions will be removed as a
follow up.</content>
<content type='xhtml'>
<div xmlns='http://www.w3.org/1999/xhtml'>
<pre>
This reverts commit 0dba5381d8c8e4cadc32a067bf2fe5e3486ae53d.

YMM rounding was removed from AVX10 whitepaper. Ref:
https://cdrdv2.intel.com/v1/dl/getContent/784343

The MINMAX and SATURATING CONVERT instructions will be removed as a
follow up.</pre>
</div>
</content>
</entry>
<entry>
<title>[X86] Ignore REX prefixes not immediately before opcode (#117299)</title>
<updated>2024-11-22T18:56:24+00:00</updated>
<author>
<name>Aiden Grossman</name>
<email>aidengrossman@google.com</email>
</author>
<published>2024-11-22T18:56:24+00:00</published>
<link rel='alternate' type='text/html' href='https://git.belthelziquor.com/llvm-project.git/commit/?id=7530e707afc60014624eb62bda9557cdc7f28dd0'/>
<id>7530e707afc60014624eb62bda9557cdc7f28dd0</id>
<content type='text'>
The Intel X86 Architecture Manual says the following:

&gt; A REX prefix is ignored, as are its individual bits, when it is not
needed
&gt; for an instruction or when it does not immediately precede the opcode
byte or
&gt; the escape opcode byte (0FH) of an instruction for which it is needed.
This
&gt; has the implication that only one REX prefix, properly located, can
affect an
&gt; instruction.

We currently do not handle these cases in the disassembler, leading to
incorrect disassembly. This patch rectifies the situation by treating
REX prefixes as standard prefixes rather than only expecting them before
the Opcode.

The motivating test case added as a test was fuzzer generated.</content>
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<pre>
The Intel X86 Architecture Manual says the following:

&gt; A REX prefix is ignored, as are its individual bits, when it is not
needed
&gt; for an instruction or when it does not immediately precede the opcode
byte or
&gt; the escape opcode byte (0FH) of an instruction for which it is needed.
This
&gt; has the implication that only one REX prefix, properly located, can
affect an
&gt; instruction.

We currently do not handle these cases in the disassembler, leading to
incorrect disassembly. This patch rectifies the situation by treating
REX prefixes as standard prefixes rather than only expecting them before
the Opcode.

The motivating test case added as a test was fuzzer generated.</pre>
</div>
</content>
</entry>
<entry>
<title>[X86] Switch to the new symbol visibility macros (#109982)</title>
<updated>2024-11-07T18:15:25+00:00</updated>
<author>
<name>Thomas Fransham</name>
<email>tfransham@gmail.com</email>
</author>
<published>2024-11-07T18:15:25+00:00</published>
<link rel='alternate' type='text/html' href='https://git.belthelziquor.com/llvm-project.git/commit/?id=7760ae7b608193a410b71df7ae7daccf2a6b09c1'/>
<id>7760ae7b608193a410b71df7ae7daccf2a6b09c1</id>
<content type='text'>
Switch LLVMInitialize* functions to new the symbol visibility macros
that will work for windows.
This is part of the work to enable LLVM_BUILD_LLVM_DYLIB and plugins on
windows.</content>
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<pre>
Switch LLVMInitialize* functions to new the symbol visibility macros
that will work for windows.
This is part of the work to enable LLVM_BUILD_LLVM_DYLIB and plugins on
windows.</pre>
</div>
</content>
</entry>
<entry>
<title>[X86][AMX] Support AMX-TRANSPOSE (#113532)</title>
<updated>2024-11-01T08:45:03+00:00</updated>
<author>
<name>Phoebe Wang</name>
<email>phoebe.wang@intel.com</email>
</author>
<published>2024-11-01T08:45:03+00:00</published>
<link rel='alternate' type='text/html' href='https://git.belthelziquor.com/llvm-project.git/commit/?id=c72a751dabff4260dcc309e48008941d51b31d21'/>
<id>c72a751dabff4260dcc309e48008941d51b31d21</id>
<content type='text'>
Ref.: https://cdrdv2.intel.com/v1/dl/getContent/671368</content>
<content type='xhtml'>
<div xmlns='http://www.w3.org/1999/xhtml'>
<pre>
Ref.: https://cdrdv2.intel.com/v1/dl/getContent/671368</pre>
</div>
</content>
</entry>
<entry>
<title>[X86][AVX10.2] Support YMM rounding new instructions (#101825)</title>
<updated>2024-08-04T13:05:45+00:00</updated>
<author>
<name>Phoebe Wang</name>
<email>phoebe.wang@intel.com</email>
</author>
<published>2024-08-04T13:05:45+00:00</published>
<link rel='alternate' type='text/html' href='https://git.belthelziquor.com/llvm-project.git/commit/?id=0dba5381d8c8e4cadc32a067bf2fe5e3486ae53d'/>
<id>0dba5381d8c8e4cadc32a067bf2fe5e3486ae53d</id>
<content type='text'>
Ref.: https://cdrdv2.intel.com/v1/dl/getContent/828965</content>
<content type='xhtml'>
<div xmlns='http://www.w3.org/1999/xhtml'>
<pre>
Ref.: https://cdrdv2.intel.com/v1/dl/getContent/828965</pre>
</div>
</content>
</entry>
<entry>
<title>Reland "[X86][AVX10.2] Support AVX10.2 option and VMPSADBW/VADDP[D,H,S] new instructions (#101452)" (#101616)</title>
<updated>2024-08-03T01:26:07+00:00</updated>
<author>
<name>Phoebe Wang</name>
<email>phoebe.wang@intel.com</email>
</author>
<published>2024-08-03T01:26:07+00:00</published>
<link rel='alternate' type='text/html' href='https://git.belthelziquor.com/llvm-project.git/commit/?id=259ca9ee9c4d9f7ba2d05db9fe05f782a865aeb5'/>
<id>259ca9ee9c4d9f7ba2d05db9fe05f782a865aeb5</id>
<content type='text'>
Ref.: https://cdrdv2.intel.com/v1/dl/getContent/828965</content>
<content type='xhtml'>
<div xmlns='http://www.w3.org/1999/xhtml'>
<pre>
Ref.: https://cdrdv2.intel.com/v1/dl/getContent/828965</pre>
</div>
</content>
</entry>
<entry>
<title>Revert "[X86][AVX10.2] Support AVX10.2 option and VMPSADBW/VADDP[D,H,S] new instructions" (#101612)</title>
<updated>2024-08-02T05:04:10+00:00</updated>
<author>
<name>Phoebe Wang</name>
<email>phoebe.wang@intel.com</email>
</author>
<published>2024-08-02T05:04:10+00:00</published>
<link rel='alternate' type='text/html' href='https://git.belthelziquor.com/llvm-project.git/commit/?id=2e0588d5e1c9e9a0936846173dbc488f462a6c2d'/>
<id>2e0588d5e1c9e9a0936846173dbc488f462a6c2d</id>
<content type='text'>
Reverts llvm/llvm-project#101452

There are several buildbot failed. Revert first.</content>
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<pre>
Reverts llvm/llvm-project#101452

There are several buildbot failed. Revert first.</pre>
</div>
</content>
</entry>
<entry>
<title>[X86][AVX10.2] Support AVX10.2 option and VMPSADBW/VADDP[D,H,S] new instructions (#101452)</title>
<updated>2024-08-02T04:10:50+00:00</updated>
<author>
<name>Phoebe Wang</name>
<email>phoebe.wang@intel.com</email>
</author>
<published>2024-08-02T04:10:50+00:00</published>
<link rel='alternate' type='text/html' href='https://git.belthelziquor.com/llvm-project.git/commit/?id=10bad2c8d7be1bbb726c536dd306da3cae2247b4'/>
<id>10bad2c8d7be1bbb726c536dd306da3cae2247b4</id>
<content type='text'>
Ref.: https://cdrdv2.intel.com/v1/dl/getContent/828965</content>
<content type='xhtml'>
<div xmlns='http://www.w3.org/1999/xhtml'>
<pre>
Ref.: https://cdrdv2.intel.com/v1/dl/getContent/828965</pre>
</div>
</content>
</entry>
<entry>
<title>[X86][MC] Not decode 0xf3 as rep prefix if it's right before REX2</title>
<updated>2024-06-13T15:26:33+00:00</updated>
<author>
<name>Shengchen Kan</name>
<email>shengchen.kan@intel.com</email>
</author>
<published>2024-06-13T15:24:03+00:00</published>
<link rel='alternate' type='text/html' href='https://git.belthelziquor.com/llvm-project.git/commit/?id=91a55cf5adbe37d33dc7b3b90de4bbb0b90761a1'/>
<id>91a55cf5adbe37d33dc7b3b90de4bbb0b90761a1</id>
<content type='text'>
This fixes https://github.com/llvm/llvm-project/issues/95412
</content>
<content type='xhtml'>
<div xmlns='http://www.w3.org/1999/xhtml'>
<pre>
This fixes https://github.com/llvm/llvm-project/issues/95412
</pre>
</div>
</content>
</entry>
<entry>
<title>[X86][MC] Support encoding/decoding for APX CCMP/CTEST (#83863)</title>
<updated>2024-03-08T12:54:33+00:00</updated>
<author>
<name>Shengchen Kan</name>
<email>shengchen.kan@intel.com</email>
</author>
<published>2024-03-08T12:54:33+00:00</published>
<link rel='alternate' type='text/html' href='https://git.belthelziquor.com/llvm-project.git/commit/?id=1ca8092e87aea58f1c3752d03c20bdfc4259e409'/>
<id>1ca8092e87aea58f1c3752d03c20bdfc4259e409</id>
<content type='text'>
APX assembly syntax recommendations:
  https://cdrdv2.intel.com/v1/dl/getContent/817241

NOTE:
The change in llvm/tools/llvm-exegesis/lib/X86/Target.cpp is for test
LLVM ::
tools/llvm-exegesis/X86/latency/latency-SETCCr-cond-codes-sweep.s

For `SETcc`, llvm-exegesis would randomly choose 1 other instruction to
test with `SETcc`, after selecting the instruction, llvm-exegesis would
check if the operand is initialized and valid, if not
`randomizeTargetMCOperand` would choose a value for invalid operand, it
misses support for condition code operand, which cause the flaky failure
after `CCMP` supported.

llvm-exegesis can choose `CCMP` without specifying ccmp feature b/c it
use `MCSubtarget` and only16/32/64 bit is considered.
llvm-exegesis doesn't choose other instructions b/c requirement in
`hasAliasingRegistersThrough`: the instruction should use GPR (defined
by `SETcc`) and define `EFLAGS` (used by `SETcc`).</content>
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<pre>
APX assembly syntax recommendations:
  https://cdrdv2.intel.com/v1/dl/getContent/817241

NOTE:
The change in llvm/tools/llvm-exegesis/lib/X86/Target.cpp is for test
LLVM ::
tools/llvm-exegesis/X86/latency/latency-SETCCr-cond-codes-sweep.s

For `SETcc`, llvm-exegesis would randomly choose 1 other instruction to
test with `SETcc`, after selecting the instruction, llvm-exegesis would
check if the operand is initialized and valid, if not
`randomizeTargetMCOperand` would choose a value for invalid operand, it
misses support for condition code operand, which cause the flaky failure
after `CCMP` supported.

llvm-exegesis can choose `CCMP` without specifying ccmp feature b/c it
use `MCSubtarget` and only16/32/64 bit is considered.
llvm-exegesis doesn't choose other instructions b/c requirement in
`hasAliasingRegistersThrough`: the instruction should use GPR (defined
by `SETcc`) and define `EFLAGS` (used by `SETcc`).</pre>
</div>
</content>
</entry>
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