llvm-project.git/llvm/lib/Target/WebAssembly/WebAssemblyInstrMemory.td, branch users/nico/python-2

[WebAssembly] Change half-precision feature name to fp16. (#105434)

2024-08-22T16:44:33+00:00

This better aligns with how the feature is being referred to and what
runtimes (V8) are calling it.

[WebAssembly] Implement prototype f32.store_f16 instruction. (#91545)

2024-05-09T22:38:13+00:00

Adds a builtin and intrinsic for the f32.store_f16 instruction.

The instruction stores an f32 value as an f16 memory. Specified at:

https://github.com/WebAssembly/half-precision/blob/29a9b9462c9285d4ccc1a5dc39214ddfd1892658/proposals/half-precision/Overview.md

Note: the current spec has f32.store_f16 as opcode 0xFD0121, but this is
incorrect and will be changed to 0xFC31 soon.

[WebAssembly] Implement prototype f32.load_f16 instruction. (#90906)

2024-05-07T18:33:10+00:00

Adds a builtin and intrinsic for the f32.load_f16 instruction.

The instruction loads an f16 value from memory and puts it in an f32.
Specified at:

https://github.com/WebAssembly/half-precision/blob/29a9b9462c9285d4ccc1a5dc39214ddfd1892658/proposals/half-precision/Overview.md

Note: the current spec has f32.load_f16 as opcode 0xFD0120, but this is
incorrect and will be changed to 0xFC30 soon.

[WebAssembly] Use ComplexPattern on remaining memory instructions

2022-12-15T10:20:06+00:00

This continues the refactoring work of selecting offset + address
operands with the AddrOpsN pattern, previously called LoadOpsN.

This is not an NFC, since constant addresses are now folded into the
offset in more places for v128.storeN_lane.

Differential Revision: https://reviews.llvm.org/D139950

[WebAssembly][NFC] Add ComplexPattern for loads

2022-12-14T12:11:30+00:00

This refactors out the offset and address operand pattern matching into
a ComplexPattern, so that one pattern fragment can match the dynamic and
static (offset) addresses in all possible positions.

Split out from D139530, which also contained an improvement to global
address folding.

Differential Revision: https://reviews.llvm.org/D139631

[WebAssembly][NFC] Convert IsWasm64 instruction field to 'bit' from string

2022-05-17T10:06:40+00:00

Extends the cleanup in D125713 to IsWasm64.

Differential Revision: https://reviews.llvm.org/D125714

[WebAssembly] Fix names of WebAssemblyWrapper SDNodes. NFC

2021-09-02T17:54:44+00:00

Other platforms all use CamelCase as normal for these wrapper nodes.

Differential Revision: https://reviews.llvm.org/D109172

[WebAssembly] Fix multiclass template parameter types. NFC.

2021-02-08T09:36:56+00:00

Fixes TableGen parser errors reported by D95874 due to incompatible types being used on multiclass templates.

Differential Revision: https://reviews.llvm.org/D96205

[WebAssembly] Implement prototype v128.load{32,64}_zero instructions

2020-08-03T20:54:00+00:00

Specified in https://github.com/WebAssembly/simd/pull/237, these
instructions load the first vector lane from memory and zero the other
lanes. Since these instructions are not officially part of the SIMD
proposal, they are only available on an opt-in basis via LLVM
intrinsics and clang builtin functions. If these instructions are
merged to the proposal, this implementation will change so that the
instructions will be generated from normal IR. At that point the
intrinsics and builtin functions would be removed.

This PR also changes the opcodes for the experimental f32x4.qfm{a,s}
instructions because their opcodes conflicted with those of the
v128.load{32,64}_zero instructions. The new opcodes were chosen to
match those used in V8.

Differential Revision: https://reviews.llvm.org/D84820

[WebAssembly] Added 64-bit memory.grow/size/copy/fill

2020-07-06T19:49:50+00:00

This covers both the existing memory functions as well as the new bulk memory proposal.
Added new test files since changes where also required in the inputs.

Also removes unused init/drop intrinsics rather than trying to make them work for 64-bit.

Differential Revision: https://reviews.llvm.org/D82821