These can be handled via the VECTOR SHIFT LEFT/RIGHT DOUBLE
family of instructions, depending on architecture level.

Fixes: https://github.com/llvm/llvm-project/issues/129955

Generate code using the VECTOR ADD COMPUTE CARRY and
VECTOR SUBTRACT COMPUTE BORROW INDICATION instructions
to implement open-coded IR with those semantics.

Handles integer vector types as well as i128.

Fixes: https://github.com/llvm/llvm-project/issues/129608

Detect (non-intrinsic) IR patterns corresponding to the semantics
of the various widening and high-word multiplication instructions.

Specifically, this is done by:
- Recognizing even/odd widening multiplication patterns in DAGCombine
- Recognizing widening multiply-and-add on top during ISel
- Implementing the standard MULHS/MUHLU IR opcodes
- Detecting high-word multiply-and-add (which common code does not)

Depending on architecture level, this can support all integer
vector types as well as the scalar i128 type.

Fixes: https://github.com/llvm/llvm-project/issues/129705

This patch adds support for the next-generation arch15
CPU architecture to the SystemZ backend.

This includes:
- Basic support for the new processor and its features.
- Detection of arch15 as host processor.
- Assembler/disassembler support for new instructions.
- Exploitation of new instructions for code generation.
- New vector (signed|unsigned|bool) __int128 data types.
- New LLVM intrinsics for certain new instructions.
- Support for low-level builtins mapped to new LLVM intrinsics.
- New high-level intrinsics in vecintrin.h.
- Indicate support by defining  __VEC__ == 10305.

Note: No currently available Z system supports the arch15
architecture.  Once new systems become available, the
official system name will be added as supported -march name.

The "Size >= 32" check probably dates back to when TableGen integers
were 32-bit. Delete it and simplify code by using `isInt`/`isUInt`.

This pr includes fixes for original pr##116642.
Implementation for __builtin_setjmp and __builtin_longjmp for SystemZ..

This reverts commit 030bbc92a705758f1131fb29cab5be6d6a27dd1f.

Implementation for __builtin_setjmp and __builtin_longjmp for SystemZ.

Enable MachineCombining for FP add, sub and mul.

In order for this to work, the default instruction selection of reg/mem opcodes is disabled for ISD nodes that carry the flags that allow reassociation. The reg/mem folding is instead done after MachineCombiner by PeepholeOptimizer. SystemZInstrInfo optimizeLoadInstr() and foldMemoryOperandImpl() ("LoadMI version") have been implemented for this purpose also by this patch.