This fixes forward an issue in PR #147427.
This patch fixes an error in which `FAKE_USE` instructions would trigger an assertion in SystemZLongBranch due to them having a size of 0 without being excepted in the assertion that each instruction, other than a set of known 0-size instruction types, should have a non-0 size. `FAKE_USE` instructions are no-op instructions that are emitted into LLVM by the `-fextend-variable-liveness` clang flag to help preserve the liveness of source variables in optimized code, and therefore they should be understood as being valid size 0 instructions.
Due to some optimization changes, INIT_UNDEF is making its way to `getInstSizeInBytes` in `llvm/lib/Target/SystemZ/SystemZLongBranch.cpp` but we do not have an exception there in the assert. Since INIT_UNDEF is described as being similar to IMPLICIT_DEF and there is a check for IMPLICIT_DEF, it seems logical to also add a check for INIT_UNDEF. --------- Co-authored-by: Tony Tao <tonytao@ca.ibm.com>
- Remove calls to pass initialization from pass constructors. - https://github.com/llvm/llvm-project/issues/111767
This PR instruments the optimization passes in the SystemZ backend with calls to `MachineFunction::substituteDebugValuesForInst` where instruction substitutions are made to instructions that may compute tracked values. Tests are also added for each of the substitutions that were inserted. Details on the individual passes follow. ### systemz-copy-physregs When a copy targets an access register, we redirect the copy via an auxiliary register. This leads to the final result being written by a newly inserted SAR instruction, rather than the original MI, so we need to update the debug value tracking to account for this. ### systemz-long-branch This pass relaxes relative branch instructions based on the actual locations of blocks. Only one of the branch instructions qualifies for debug value tracking: BRCT, i.e. branch-relative-on-count, which subtracts 1 from a register and branches if the result is not zero. This is relaxed into an add-immediate and a conditional branch, so any `debug-instr-number` present must move to the add-immediate instruction. ### systemz-post-rewrite This pass replaces `LOCRMux` and `SELRMux` pseudoinstructions with either the real versions of those instructions, or with branching programs that implement the intent of the Pseudo. In all these cases, any `debug-instr-number` attached to the pseudo needs to be reallocated to the appropriate instruction in the result, either LOCR, SELR, or a COPY. ### systemz-elim-compare Similar to systemz-long-branch, for this pass, only few substitutions are necessary, since it mainly deals with conditional branch instructions. The only exceptiona are again branch-relative-on-count, as it modifies a counter as part of the instruction, as well as any of the load instructions that are affected.
This pr includes fixes for original pr##116642. Implementation for __builtin_setjmp and __builtin_longjmp for SystemZ..
This reverts commit 030bbc92a705758f1131fb29cab5be6d6a27dd1f.
Implementation for __builtin_setjmp and __builtin_longjmp for SystemZ.
This is a follow up to D141317 which extends the common code to include a target independent pseudo instruction. This is an alternative to (subset of) D92842 which tries to be as close to NFC as possible. A couple things to call out. * The test change in X86 is because we loose the scheduling information on the instruction. However, I think this was actually a bug in x86 since no instruction was emitted for a MEMBARRIER. Concluding that a meta instruction has latency just seems wrong? * I intentionally left some parts of D92842 out. Specifically, several of the changes in the X86 code (data independence and outlining) appear functional, and likely worthy of their own review. Additionally, I'm not handling ARM/AArch64 at all. Those targets need the ordering whereas none of the others do. I want to get this in and tested before retrofitting in ordering to support those targets. Differential Revision: https://reviews.llvm.org/D141408