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<title>llvm-project.git/llvm/lib/Target/SystemZ/SystemZInstrInfo.td, branch users/nico/python-2</title>
<subtitle>Unnamed repository; edit this file 'description' to name the repository.
</subtitle>
<link rel='alternate' type='text/html' href='https://git.belthelziquor.com/llvm-project.git/'/>
<entry>
<title>[SystemZ] Implement basic `isCopyInstrImpl` (#132903)</title>
<updated>2025-03-25T14:00:54+00:00</updated>
<author>
<name>Dominik Steenken</name>
<email>dost@de.ibm.com</email>
</author>
<published>2025-03-25T14:00:54+00:00</published>
<link rel='alternate' type='text/html' href='https://git.belthelziquor.com/llvm-project.git/commit/?id=c0a7ccb59acfe90de38c580f52f2691c00f7ea9c'/>
<id>c0a7ccb59acfe90de38c580f52f2691c00f7ea9c</id>
<content type='text'>
As a first step toward implementing SystemZ support for instr-ref-based
debug info tracking, this commit adds a basic implementation for the
previously absent `SystemZInstrInfo::isCopyInstrImpl`.

This is accomplished by adding a new flag called `isMoveReg` on the
relevant instructions and calling upon that bit of information to
implement the function. Which instructions to add the flag to was based
on the implementation of `SystemZInstrInfo::copyPhysReg`. The full list
of instructions is as follows:

#### General-Purpose Registers
- `lr`
- `lgr`
#### Floating Point Registers
- `ler`
- `ldr`
- `lxr`
#### Vector Registers
- `vlr`</content>
<content type='xhtml'>
<div xmlns='http://www.w3.org/1999/xhtml'>
<pre>
As a first step toward implementing SystemZ support for instr-ref-based
debug info tracking, this commit adds a basic implementation for the
previously absent `SystemZInstrInfo::isCopyInstrImpl`.

This is accomplished by adding a new flag called `isMoveReg` on the
relevant instructions and calling upon that bit of information to
implement the function. Which instructions to add the flag to was based
on the implementation of `SystemZInstrInfo::copyPhysReg`. The full list
of instructions is as follows:

#### General-Purpose Registers
- `lr`
- `lgr`
#### Floating Point Registers
- `ler`
- `ldr`
- `lxr`
#### Vector Registers
- `vlr`</pre>
</div>
</content>
</entry>
<entry>
<title>[SystemZ] Make I5 operand of R[INOX]SGB(Z)? optional (#129512)</title>
<updated>2025-03-04T17:53:36+00:00</updated>
<author>
<name>Dominik Steenken</name>
<email>dost@de.ibm.com</email>
</author>
<published>2025-03-04T17:53:36+00:00</published>
<link rel='alternate' type='text/html' href='https://git.belthelziquor.com/llvm-project.git/commit/?id=0f869cc336a8155da7b095d0ca704dc8b6777092'/>
<id>0f869cc336a8155da7b095d0ca704dc8b6777092</id>
<content type='text'>
The I5 operand of the instructions in RIE-f format is optional and
assumed 0 when not specified. This was not properly modeled thus far,
and is corrected with this PR. In addition, assembly and disassembly
tests are updated to reflect these changes</content>
<content type='xhtml'>
<div xmlns='http://www.w3.org/1999/xhtml'>
<pre>
The I5 operand of the instructions in RIE-f format is optional and
assumed 0 when not specified. This was not properly modeled thus far,
and is corrected with this PR. In addition, assembly and disassembly
tests are updated to reflect these changes</pre>
</div>
</content>
</entry>
<entry>
<title>[SystemZ] Change operand type for CKSM intrstruction. (#129572)</title>
<updated>2025-03-03T21:17:29+00:00</updated>
<author>
<name>Kai Nacke</name>
<email>kai.peter.nacke@ibm.com</email>
</author>
<published>2025-03-03T21:17:29+00:00</published>
<link rel='alternate' type='text/html' href='https://git.belthelziquor.com/llvm-project.git/commit/?id=eee3db5421040cfc3eae6e92ed714650a6f741fa'/>
<id>eee3db5421040cfc3eae6e92ed714650a6f741fa</id>
<content type='text'>
The current definition of the CKSM instruction uses GR64 for the first
operand. However, according to the Principles Of Operation the bits 0-31
of the first operand always remain unchanged. This PR changes the first
operand to GR32 to model this.
This has no further implication as this instruction is not used during
code generation.</content>
<content type='xhtml'>
<div xmlns='http://www.w3.org/1999/xhtml'>
<pre>
The current definition of the CKSM instruction uses GR64 for the first
operand. However, according to the Principles Of Operation the bits 0-31
of the first operand always remain unchanged. This PR changes the first
operand to GR32 to model this.
This has no further implication as this instruction is not used during
code generation.</pre>
</div>
</content>
</entry>
<entry>
<title>[SystemZ] Add support for new cpu architecture - arch15</title>
<updated>2025-01-20T18:30:21+00:00</updated>
<author>
<name>Ulrich Weigand</name>
<email>ulrich.weigand@de.ibm.com</email>
</author>
<published>2025-01-20T18:23:18+00:00</published>
<link rel='alternate' type='text/html' href='https://git.belthelziquor.com/llvm-project.git/commit/?id=8424bf207efd89eacf2fe893b67be98d535e1db6'/>
<id>8424bf207efd89eacf2fe893b67be98d535e1db6</id>
<content type='text'>
This patch adds support for the next-generation arch15
CPU architecture to the SystemZ backend.

This includes:
- Basic support for the new processor and its features.
- Detection of arch15 as host processor.
- Assembler/disassembler support for new instructions.
- Exploitation of new instructions for code generation.
- New vector (signed|unsigned|bool) __int128 data types.
- New LLVM intrinsics for certain new instructions.
- Support for low-level builtins mapped to new LLVM intrinsics.
- New high-level intrinsics in vecintrin.h.
- Indicate support by defining  __VEC__ == 10305.

Note: No currently available Z system supports the arch15
architecture.  Once new systems become available, the
official system name will be added as supported -march name.
</content>
<content type='xhtml'>
<div xmlns='http://www.w3.org/1999/xhtml'>
<pre>
This patch adds support for the next-generation arch15
CPU architecture to the SystemZ backend.

This includes:
- Basic support for the new processor and its features.
- Detection of arch15 as host processor.
- Assembler/disassembler support for new instructions.
- Exploitation of new instructions for code generation.
- New vector (signed|unsigned|bool) __int128 data types.
- New LLVM intrinsics for certain new instructions.
- Support for low-level builtins mapped to new LLVM intrinsics.
- New high-level intrinsics in vecintrin.h.
- Indicate support by defining  __VEC__ == 10305.

Note: No currently available Z system supports the arch15
architecture.  Once new systems become available, the
official system name will be added as supported -march name.
</pre>
</div>
</content>
</entry>
<entry>
<title>[TableGen][SystemZ] Correctly check the range of a leaf immediate (#119931)</title>
<updated>2024-12-14T10:58:23+00:00</updated>
<author>
<name>Sergei Barannikov</name>
<email>barannikov88@gmail.com</email>
</author>
<published>2024-12-14T10:58:23+00:00</published>
<link rel='alternate' type='text/html' href='https://git.belthelziquor.com/llvm-project.git/commit/?id=97c3c32372bb8478c53ab9469585c7c6e531cbd2'/>
<id>97c3c32372bb8478c53ab9469585c7c6e531cbd2</id>
<content type='text'>
The "Size &gt;= 32" check probably dates back to when TableGen integers
were 32-bit. Delete it and simplify code by using `isInt`/`isUInt`.</content>
<content type='xhtml'>
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<pre>
The "Size &gt;= 32" check probably dates back to when TableGen integers
were 32-bit. Delete it and simplify code by using `isInt`/`isUInt`.</pre>
</div>
</content>
</entry>
<entry>
<title>SystemZ: Add support for __builtin_setjmp and __builtin_longjmp. (#119257)</title>
<updated>2024-12-10T18:50:51+00:00</updated>
<author>
<name>anoopkg6</name>
<email>anoop.kumar6@ibm.com</email>
</author>
<published>2024-12-10T18:50:51+00:00</published>
<link rel='alternate' type='text/html' href='https://git.belthelziquor.com/llvm-project.git/commit/?id=dc04d414df9c243bb90d7cfc683a632a2c032c62'/>
<id>dc04d414df9c243bb90d7cfc683a632a2c032c62</id>
<content type='text'>
This pr includes fixes for original pr##116642.
Implementation for __builtin_setjmp and __builtin_longjmp for SystemZ..</content>
<content type='xhtml'>
<div xmlns='http://www.w3.org/1999/xhtml'>
<pre>
This pr includes fixes for original pr##116642.
Implementation for __builtin_setjmp and __builtin_longjmp for SystemZ..</pre>
</div>
</content>
</entry>
<entry>
<title>Revert "[SystemZ] Add support for __builtin_setjmp and __builtin_longjmp (#116642)"</title>
<updated>2024-12-06T23:55:54+00:00</updated>
<author>
<name>Ulrich Weigand</name>
<email>ulrich.weigand@de.ibm.com</email>
</author>
<published>2024-12-06T23:55:54+00:00</published>
<link rel='alternate' type='text/html' href='https://git.belthelziquor.com/llvm-project.git/commit/?id=8787bc72a61aa43a6e937647b6797ddb2ff287d2'/>
<id>8787bc72a61aa43a6e937647b6797ddb2ff287d2</id>
<content type='text'>
This reverts commit 030bbc92a705758f1131fb29cab5be6d6a27dd1f.
</content>
<content type='xhtml'>
<div xmlns='http://www.w3.org/1999/xhtml'>
<pre>
This reverts commit 030bbc92a705758f1131fb29cab5be6d6a27dd1f.
</pre>
</div>
</content>
</entry>
<entry>
<title>[SystemZ] Add support for __builtin_setjmp and __builtin_longjmp (#116642)</title>
<updated>2024-12-06T22:33:33+00:00</updated>
<author>
<name>anoopkg6</name>
<email>anoop.kumar6@ibm.com</email>
</author>
<published>2024-12-06T22:33:33+00:00</published>
<link rel='alternate' type='text/html' href='https://git.belthelziquor.com/llvm-project.git/commit/?id=030bbc92a705758f1131fb29cab5be6d6a27dd1f'/>
<id>030bbc92a705758f1131fb29cab5be6d6a27dd1f</id>
<content type='text'>
Implementation for __builtin_setjmp and __builtin_longjmp for SystemZ.</content>
<content type='xhtml'>
<div xmlns='http://www.w3.org/1999/xhtml'>
<pre>
Implementation for __builtin_setjmp and __builtin_longjmp for SystemZ.</pre>
</div>
</content>
</entry>
<entry>
<title>[SystemZ] Use nop mnemonics for disassembly</title>
<updated>2024-12-03T17:51:20+00:00</updated>
<author>
<name>Ulrich Weigand</name>
<email>ulrich.weigand@de.ibm.com</email>
</author>
<published>2024-12-03T17:49:46+00:00</published>
<link rel='alternate' type='text/html' href='https://git.belthelziquor.com/llvm-project.git/commit/?id=d1f4f6368064d8d7bf09fbd5be8d74846d532c30'/>
<id>d1f4f6368064d8d7bf09fbd5be8d74846d532c30</id>
<content type='text'>
To match the behavior of GNU binutils, output the nop family
of mnemonic aliases when disassembling.
</content>
<content type='xhtml'>
<div xmlns='http://www.w3.org/1999/xhtml'>
<pre>
To match the behavior of GNU binutils, output the nop family
of mnemonic aliases when disassembling.
</pre>
</div>
</content>
</entry>
<entry>
<title>[SystemZ] Rename SystemZ ATT Asm dialect to GNU Asm dialect (#112800)</title>
<updated>2024-10-18T14:26:50+00:00</updated>
<author>
<name>tltao</name>
<email>tony.le.tao@gmail.com</email>
</author>
<published>2024-10-18T14:26:50+00:00</published>
<link rel='alternate' type='text/html' href='https://git.belthelziquor.com/llvm-project.git/commit/?id=783901bd2008cbe835ef394f6c3147013604e95f'/>
<id>783901bd2008cbe835ef394f6c3147013604e95f</id>
<content type='text'>
The ATT assembler dialect on SystemZ seems to have been taken from the
existing ATT/Intel code. However, on SystemZ, ATT does not hold any
meaning. In reality, we are splitting the difference between GNU Asm
syntax and HLASM Asm syntax, so it makes sense to rename ATT to GNU
instead.

Co-authored-by: Tony Tao &lt;tonytao@ca.ibm.com&gt;</content>
<content type='xhtml'>
<div xmlns='http://www.w3.org/1999/xhtml'>
<pre>
The ATT assembler dialect on SystemZ seems to have been taken from the
existing ATT/Intel code. However, on SystemZ, ATT does not hold any
meaning. In reality, we are splitting the difference between GNU Asm
syntax and HLASM Asm syntax, so it makes sense to rename ATT to GNU
instead.

Co-authored-by: Tony Tao &lt;tonytao@ca.ibm.com&gt;</pre>
</div>
</content>
</entry>
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