The I5 operand of the instructions in RIE-f format is optional and
assumed 0 when not specified. This was not properly modeled thus far,
and is corrected with this PR. In addition, assembly and disassembly
tests are updated to reflect these changes

This patch adds support for the next-generation arch15
CPU architecture to the SystemZ backend.

This includes:
- Basic support for the new processor and its features.
- Detection of arch15 as host processor.
- Assembler/disassembler support for new instructions.
- Exploitation of new instructions for code generation.
- New vector (signed|unsigned|bool) __int128 data types.
- New LLVM intrinsics for certain new instructions.
- Support for low-level builtins mapped to new LLVM intrinsics.
- New high-level intrinsics in vecintrin.h.
- Indicate support by defining  __VEC__ == 10305.

Note: No currently available Z system supports the arch15
architecture.  Once new systems become available, the
official system name will be added as supported -march name.

To match the behavior of GNU binutils, output the nop family
of mnemonic aliases when disassembling.

Now that the GNU and HLASM `InstPrinter` paths are separated in
https://github.com/llvm/llvm-project/pull/112975, differentiate between
them in `SystemZInstrFormats.td`.

The main difference are:
- Tabs converted to space
- Remove space after comma for instruction operands

---------

Co-authored-by: Tony Tao <tonytao@ca.ibm.com>

The ATT assembler dialect on SystemZ seems to have been taken from the
existing ATT/Intel code. However, on SystemZ, ATT does not hold any
meaning. In reality, we are splitting the difference between GNU Asm
syntax and HLASM Asm syntax, so it makes sense to rename ATT to GNU
instead.

Co-authored-by: Tony Tao <tonytao@ca.ibm.com>

This PR adds a number of thus-far missing extended mnemonics to the
assembler and disassembler for SystemZ.

The following mnemonics have been added and are supported for the
assembler and disassembler:

- `NOP(R)?`
- `LFI`
- `RISBG(N)?Z`

The following mnemonics have been added and are supported for the
assembler only:

- `JC(TH)?`
- `LLG(F|H)I`
- `NOT(G)?R`

- Instead of lowering float/double ISD::ATOMIC_LOAD / ISD::ATOMIC_STORE
nodes to regular LOAD/STORE nodes, make them legal and select those nodes
properly instead. This avoids exposing them to the DAGCombiner.

- AtomicExpand pass no longer casts float/double atomic load/stores to integer
  (FP128 is still casted).

The usage of FP Load and Test instructions as a comparison against zero
with the assumption that the dest reg will always reflect the source reg is
actually incorrect: Unfortunately, a SNaN will be converted to a QNaN, so the
instruction may actually change the value as opposed to being a pure register
move with a test.

This patch
- changes instruction selection to always emit FP LT with a scratch def
  reg, which will typically be allocated to the same reg if dead.
- Removes the conversions into FP LT in SystemZElimcompare.

Let the AtomicExpand pass do more of the job of expanding
AtomicRMWInst:s in order to simplify the handling in the backend.

The only cases that the backend needs to handle itself are those of
subword size (8/16 bits) and those directly corresponding to a target
instruction.

Prepare for removing the MemOpsEmitted workaround for symbolic
displacements by letting TableGen know about the offsets of the
displacement sub-operands within the instruction.

There are alternative ways to do this that were tried and rejected:

- Creating encoders and decoders for each possible displacement offset.
  This is too repetitive.

- Use VarLenCodeEmitter [1]. The resulting diff is quite large.

Instead, use the named sub-operand support introduced by commit
a538d1f13a13 ("[TableGen][CodeEmitterGen] Allow local names for
sub-operands in a operand list.").

Describe instruction encodings in terms of sub-operands instead of
operands (e.g. B, D, L vs BDL) - this also better matches the pictures
from the Principles of Operation. Decompose operands into sub-operands
using the new (bdaddr12only $B1, $D1):$BD1 syntax. Replace the
encoders and the decoders of the operands with these of the
sub-operands.

Since DecodeADDR64BitRegisterClass() is now used for bases and indices,
change it to return NoRegister when decoding 0. This also changes the
disassembly of some instructions, e.g., br %r0 becomes br 0. Since this
better captures the instruction semantics, namely, that the value of
%r0 is not used, keep this change and update the tests.

[1] https://m680x0.github.io/blog/2022/02/varlen-encoder.html

Reviewed By: uweigand

Differential Revision: https://reviews.llvm.org/D155194