Add a DAGCombine for FCOPYSIGN that removes the rounding which is never needed as the sign bit is already in the correct place. This helps in particular the rounding to f16 case which needs a libcall. Also remove the roundings for other FP VTs and simplify the CPSDR patterns correspondingly. fp-copysign-03.ll test updated, now also covering the other FP VT combinations.
This can be done directly with the (64-bit) target instruction as only the sign bit is changed.
- _Float16 is now accepted by Clang. - The half IR type is fully handled by the backend. - These values are passed in FP registers and converted to/from float around each operation. - Compiler-rt conversion functions are now built for s390x including the missing extendhfdf2 which was added. Fixes #50374
As a first step toward implementing SystemZ support for instr-ref-based debug info tracking, this commit adds a basic implementation for the previously absent `SystemZInstrInfo::isCopyInstrImpl`. This is accomplished by adding a new flag called `isMoveReg` on the relevant instructions and calling upon that bit of information to implement the function. Which instructions to add the flag to was based on the implementation of `SystemZInstrInfo::copyPhysReg`. The full list of instructions is as follows: #### General-Purpose Registers - `lr` - `lgr` #### Floating Point Registers - `ler` - `ldr` - `lxr` #### Vector Registers - `vlr`
This is straightforward as we already had all the necessary instructions, they simply were not wired up. Also allows implementing the vec_round intrinsic via the standard llvm.roundeven IR instead of a platform intrinsic now.
Enable MachineCombining for FP add, sub and mul.
In order for this to work, the default instruction selection of reg/mem opcodes is disabled for ISD nodes that carry the flags that allow reassociation. The reg/mem folding is instead done after MachineCombiner by PeepholeOptimizer. SystemZInstrInfo optimizeLoadInstr() and foldMemoryOperandImpl() ("LoadMI version") have been implemented for this purpose also by this patch.
- Instead of lowering float/double ISD::ATOMIC_LOAD / ISD::ATOMIC_STORE nodes to regular LOAD/STORE nodes, make them legal and select those nodes properly instead. This avoids exposing them to the DAGCombiner. - AtomicExpand pass no longer casts float/double atomic load/stores to integer (FP128 is still casted).
The usage of FP Load and Test instructions as a comparison against zero with the assumption that the dest reg will always reflect the source reg is actually incorrect: Unfortunately, a SNaN will be converted to a QNaN, so the instruction may actually change the value as opposed to being a pure register move with a test. This patch - changes instruction selection to always emit FP LT with a scratch def reg, which will typically be allocated to the same reg if dead. - Removes the conversions into FP LT in SystemZElimcompare.
A rare case where coalescing resulted in a hh32 (high32 of high64 of vector register) subreg usage caused getSubReg() to fail as the vector reg does not have that subreg in its subregs list, but rather h32 which was expected to also act as hh32. See link below for the discussion when solving this. Patch By: critson Reviewed By: uweigand Fixes: https://github.com/llvm/llvm-project/issues/61390
This patch fixes the bug that consisted of treating variable / immediate length mem operations (such as memcpy, memset, ...) differently. The variable length case needs to have the length minus 1 passed due to the use of EXRL target instructions. However, the DAGCombiner can convert a register length argument into a constant one, and whenever that happened one byte too little would end up being performed. This is also a refactorization by reducing the number of opcodes and variants involved. For any opcode (variable or constant length), only the length minus one is passed on to the ISD node. The rest of the logic is now instead handled during isel pseudo expansion. Review: Ulrich Weigand Differential Revision: https://reviews.llvm.org/D111729