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<title>llvm-project.git/llvm/lib/Target/SystemZ/SystemZISelDAGToDAG.cpp, branch users/nico/python-2</title>
<subtitle>Unnamed repository; edit this file 'description' to name the repository.
</subtitle>
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<entry>
<title>[SystemZ] Add support for 16-bit floating point. (#109164)</title>
<updated>2025-04-16T18:02:56+00:00</updated>
<author>
<name>Jonas Paulsson</name>
<email>paulson1@linux.ibm.com</email>
</author>
<published>2025-04-16T18:02:56+00:00</published>
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<id>6d03f51f0c59171f1ec3c5cc5c1fe71c30956273</id>
<content type='text'>
- _Float16 is now accepted by Clang.

- The half IR type is fully handled by the backend.

- These values are passed in FP registers and converted to/from float around
  each operation.

- Compiler-rt conversion functions are now built for s390x including the missing
  extendhfdf2 which was added.

Fixes #50374</content>
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<pre>
- _Float16 is now accepted by Clang.

- The half IR type is fully handled by the backend.

- These values are passed in FP registers and converted to/from float around
  each operation.

- Compiler-rt conversion functions are now built for s390x including the missing
  extendhfdf2 which was added.

Fixes #50374</pre>
</div>
</content>
</entry>
<entry>
<title>[SDAG] Use BatchAAResults for querying alias analysis (AA) results (#123934)</title>
<updated>2025-01-23T09:16:09+00:00</updated>
<author>
<name>Benjamin Maxwell</name>
<email>benjamin.maxwell@arm.com</email>
</author>
<published>2025-01-23T09:16:09+00:00</published>
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<id>778138114e9e42e28fcb51c0a38224e667a3790c</id>
<content type='text'>
Once we get to SelectionDAG the IR should not be changing anymore, so we
can use BatchAAResults rather than AAResults to cache AA queries.

This should be a NFC change for targets that enable AA during codegen
(such as AArch64), but also give a nice compile-time improvement in some
cases. See:
https://github.com/llvm/llvm-project/pull/123787#issuecomment-2606797041

Note: This follows Nikita's suggestion on #123787.</content>
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<pre>
Once we get to SelectionDAG the IR should not be changing anymore, so we
can use BatchAAResults rather than AAResults to cache AA queries.

This should be a NFC change for targets that enable AA during codegen
(such as AArch64), but also give a nice compile-time improvement in some
cases. See:
https://github.com/llvm/llvm-project/pull/123787#issuecomment-2606797041

Note: This follows Nikita's suggestion on #123787.</pre>
</div>
</content>
</entry>
<entry>
<title>[SystemZ] Add support for new cpu architecture - arch15</title>
<updated>2025-01-20T18:30:21+00:00</updated>
<author>
<name>Ulrich Weigand</name>
<email>ulrich.weigand@de.ibm.com</email>
</author>
<published>2025-01-20T18:23:18+00:00</published>
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<id>8424bf207efd89eacf2fe893b67be98d535e1db6</id>
<content type='text'>
This patch adds support for the next-generation arch15
CPU architecture to the SystemZ backend.

This includes:
- Basic support for the new processor and its features.
- Detection of arch15 as host processor.
- Assembler/disassembler support for new instructions.
- Exploitation of new instructions for code generation.
- New vector (signed|unsigned|bool) __int128 data types.
- New LLVM intrinsics for certain new instructions.
- Support for low-level builtins mapped to new LLVM intrinsics.
- New high-level intrinsics in vecintrin.h.
- Indicate support by defining  __VEC__ == 10305.

Note: No currently available Z system supports the arch15
architecture.  Once new systems become available, the
official system name will be added as supported -march name.
</content>
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<pre>
This patch adds support for the next-generation arch15
CPU architecture to the SystemZ backend.

This includes:
- Basic support for the new processor and its features.
- Detection of arch15 as host processor.
- Assembler/disassembler support for new instructions.
- Exploitation of new instructions for code generation.
- New vector (signed|unsigned|bool) __int128 data types.
- New LLVM intrinsics for certain new instructions.
- Support for low-level builtins mapped to new LLVM intrinsics.
- New high-level intrinsics in vecintrin.h.
- Indicate support by defining  __VEC__ == 10305.

Note: No currently available Z system supports the arch15
architecture.  Once new systems become available, the
official system name will be added as supported -march name.
</pre>
</div>
</content>
</entry>
<entry>
<title>[SelectionDAG] Add SDNode::user_begin() and use it in some places (#120509)</title>
<updated>2024-12-19T06:13:04+00:00</updated>
<author>
<name>Craig Topper</name>
<email>craig.topper@sifive.com</email>
</author>
<published>2024-12-19T06:13:04+00:00</published>
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<id>bd261ecc5aeefd62150cb5f04e4a4f0cb7a12e1c</id>
<content type='text'>
Most of these are just places that want the first user and aren't
iterating over the whole list.

While there I changed some use_size() == 1 to hasOneUse() which
is more efficient.

This is part of an effort to rename use_iterator to user_iterator
and provide a use_iterator that dereferences to SDUse&amp;. This patch
helps reduce the diff on later patches.</content>
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<pre>
Most of these are just places that want the first user and aren't
iterating over the whole list.

While there I changed some use_size() == 1 to hasOneUse() which
is more efficient.

This is part of an effort to rename use_iterator to user_iterator
and provide a use_iterator that dereferences to SDUse&amp;. This patch
helps reduce the diff on later patches.</pre>
</div>
</content>
</entry>
<entry>
<title>[SelectionDAG] Rename SDNode::uses() to users(). (#120499)</title>
<updated>2024-12-19T04:09:33+00:00</updated>
<author>
<name>Craig Topper</name>
<email>craig.topper@sifive.com</email>
</author>
<published>2024-12-19T04:09:33+00:00</published>
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<id>104ad9258a0f93a969bf7a85ebc0c7d9c533edf1</id>
<content type='text'>
This function is most often used in range based loops or algorithms
where the iterator is implicitly dereferenced. The dereference returns
an SDNode * of the user rather than SDUse * so users() is a better name.

I've long beeen annoyed that we can't write a range based loop over
SDUse when we need getOperandNo. I plan to rename use_iterator to
user_iterator and add a use_iterator that returns SDUse&amp; on dereference.
This will make it more like IR.</content>
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<pre>
This function is most often used in range based loops or algorithms
where the iterator is implicitly dereferenced. The dereference returns
an SDNode * of the user rather than SDUse * so users() is a better name.

I've long beeen annoyed that we can't write a range based loop over
SDUse when we need getOperandNo. I plan to rename use_iterator to
user_iterator and add a use_iterator that returns SDUse&amp; on dereference.
This will make it more like IR.</pre>
</div>
</content>
</entry>
<entry>
<title>[SystemZ] Use getSignedConstant() where necessary (#117181)</title>
<updated>2024-11-25T08:47:49+00:00</updated>
<author>
<name>Nikita Popov</name>
<email>npopov@redhat.com</email>
</author>
<published>2024-11-25T08:47:49+00:00</published>
<link rel='alternate' type='text/html' href='https://git.belthelziquor.com/llvm-project.git/commit/?id=815a1bb53a9bb753f9aea177135150b23012550f'/>
<id>815a1bb53a9bb753f9aea177135150b23012550f</id>
<content type='text'>
This will avoid assertion failures once we disable implicit truncation
in getConstant().

Inside adjustSubwordCmp() I ended up suppressing the issue with an
explicit cast, because this code deals with a mix of unsigned and signed
immediates.</content>
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<pre>
This will avoid assertion failures once we disable implicit truncation
in getConstant().

Inside adjustSubwordCmp() I ended up suppressing the issue with an
explicit cast, because this code deals with a mix of unsigned and signed
immediates.</pre>
</div>
</content>
</entry>
<entry>
<title>[IR] Add getDataLayout() helpers to Function and GlobalValue (#96919)</title>
<updated>2024-06-28T06:36:49+00:00</updated>
<author>
<name>Nikita Popov</name>
<email>npopov@redhat.com</email>
</author>
<published>2024-06-28T06:36:49+00:00</published>
<link rel='alternate' type='text/html' href='https://git.belthelziquor.com/llvm-project.git/commit/?id=9df71d7673b5c98e1032d01be83724a45b42fafc'/>
<id>9df71d7673b5c98e1032d01be83724a45b42fafc</id>
<content type='text'>
Similar to https://github.com/llvm/llvm-project/pull/96902, this adds
`getDataLayout()` helpers to Function and GlobalValue, replacing the
current `getParent()-&gt;getDataLayout()` pattern.</content>
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<pre>
Similar to https://github.com/llvm/llvm-project/pull/96902, this adds
`getDataLayout()` helpers to Function and GlobalValue, replacing the
current `getParent()-&gt;getDataLayout()` pattern.</pre>
</div>
</content>
</entry>
<entry>
<title>Reland "[NewPM][CodeGen] Port selection dag isel to new pass manager" (#94149)</title>
<updated>2024-06-04T00:10:58+00:00</updated>
<author>
<name>paperchalice</name>
<email>liujunchang97@outlook.com</email>
</author>
<published>2024-06-04T00:10:58+00:00</published>
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<id>7652a59407018c057cdc1163c9f64b5b6f0954eb</id>
<content type='text'>
- Fix build with `EXPENSIVE_CHECKS`
- Remove unused `PassName::ID` to resolve warning
- Mark `~SelectionDAGISel` virtual so AArch64 backend can work properly</content>
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<pre>
- Fix build with `EXPENSIVE_CHECKS`
- Remove unused `PassName::ID` to resolve warning
- Mark `~SelectionDAGISel` virtual so AArch64 backend can work properly</pre>
</div>
</content>
</entry>
<entry>
<title>Revert "[NewPM][CodeGen] Port selection dag isel to new pass manager" (#94146)</title>
<updated>2024-06-02T06:31:52+00:00</updated>
<author>
<name>paperchalice</name>
<email>liujunchang97@outlook.com</email>
</author>
<published>2024-06-02T06:31:52+00:00</published>
<link rel='alternate' type='text/html' href='https://git.belthelziquor.com/llvm-project.git/commit/?id=8917afaf0ec2ebe390284e3727e720eaf97967eb'/>
<id>8917afaf0ec2ebe390284e3727e720eaf97967eb</id>
<content type='text'>
This reverts commit de37c06f01772e02465ccc9f538894c76d89a7a1 to
de37c06f01772e02465ccc9f538894c76d89a7a1

It still breaks EXPENSIVE_CHECKS build. Sorry.</content>
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<pre>
This reverts commit de37c06f01772e02465ccc9f538894c76d89a7a1 to
de37c06f01772e02465ccc9f538894c76d89a7a1

It still breaks EXPENSIVE_CHECKS build. Sorry.</pre>
</div>
</content>
</entry>
<entry>
<title>[NewPM][CodeGen] Port selection dag isel to new pass manager (#83567)</title>
<updated>2024-06-02T01:12:33+00:00</updated>
<author>
<name>paperchalice</name>
<email>liujunchang97@outlook.com</email>
</author>
<published>2024-06-02T01:12:33+00:00</published>
<link rel='alternate' type='text/html' href='https://git.belthelziquor.com/llvm-project.git/commit/?id=d2cdc8ab45d74f8691f73cb5a2b8c431585cd449'/>
<id>d2cdc8ab45d74f8691f73cb5a2b8c431585cd449</id>
<content type='text'>
Port selection dag isel to new pass manager.
Only `AMDGPU` and `X86` support new pass version. `-verify-machineinstrs` in new pass manager belongs to verify instrumentation, it is enabled by default.</content>
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<pre>
Port selection dag isel to new pass manager.
Only `AMDGPU` and `X86` support new pass version. `-verify-machineinstrs` in new pass manager belongs to verify instrumentation, it is enabled by default.</pre>
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