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<title>llvm-project.git/llvm/lib/Target/SystemZ/SystemZElimCompare.cpp, branch main</title>
<subtitle>Unnamed repository; edit this file 'description' to name the repository.
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<entry>
<title>[NFC][CodeGen] Adopt MachineFunctionProperties convenience accessors (#141101)</title>
<updated>2025-05-23T15:30:29+00:00</updated>
<author>
<name>Rahul Joshi</name>
<email>rjoshi@nvidia.com</email>
</author>
<published>2025-05-23T15:30:29+00:00</published>
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<pre>
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<entry>
<title>[NFC][LLVM][SystemZ] Cleanup pass initialization for SystemZ (#134450)</title>
<updated>2025-04-08T01:08:55+00:00</updated>
<author>
<name>Rahul Joshi</name>
<email>rjoshi@nvidia.com</email>
</author>
<published>2025-04-08T01:08:55+00:00</published>
<link rel='alternate' type='text/html' href='https://git.belthelziquor.com/llvm-project.git/commit/?id=80fde75dc6c50a7d32f6dbfda9a6f2c24890b5cc'/>
<id>80fde75dc6c50a7d32f6dbfda9a6f2c24890b5cc</id>
<content type='text'>
- Remove calls to pass initialization from pass constructors.
- https://github.com/llvm/llvm-project/issues/111767</content>
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<pre>
- Remove calls to pass initialization from pass constructors.
- https://github.com/llvm/llvm-project/issues/111767</pre>
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</content>
</entry>
<entry>
<title>[SystemZ, DebugInfo] Instrument SystemZ backend passes for Instr-Ref DebugInfo (#133061)</title>
<updated>2025-03-31T17:30:06+00:00</updated>
<author>
<name>Dominik Steenken</name>
<email>dost@de.ibm.com</email>
</author>
<published>2025-03-31T17:30:06+00:00</published>
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<id>e9a3ea2218b754a96be4f44240c3f8ee9cbd26c9</id>
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This PR instruments the optimization passes in the SystemZ backend with
calls to `MachineFunction::substituteDebugValuesForInst` where
instruction substitutions are made to instructions that may compute
tracked values.

Tests are also added for each of the substitutions that were inserted.
Details on the individual passes follow.

### systemz-copy-physregs
When a copy targets an access register, we redirect the copy via an
auxiliary register. This leads to the final result being written by a
newly inserted SAR instruction, rather than the original MI, so we need
to update the debug value tracking to account for this.

### systemz-long-branch
This pass relaxes relative branch instructions based on the actual
locations of blocks. Only one of the branch instructions qualifies for
debug value tracking: BRCT, i.e. branch-relative-on-count, which
subtracts 1 from a register and branches if the result is not zero. This
is relaxed into an add-immediate and a conditional branch, so any
`debug-instr-number` present must move to the add-immediate instruction.

### systemz-post-rewrite
This pass replaces `LOCRMux` and `SELRMux` pseudoinstructions with
either the real versions of those instructions, or with branching
programs that implement the intent of the Pseudo. In all these cases,
any `debug-instr-number` attached to the pseudo needs to be reallocated
to the appropriate instruction in the result, either LOCR, SELR, or a
COPY.

### systemz-elim-compare
Similar to systemz-long-branch, for this pass, only few substitutions
are necessary, since it mainly deals with conditional branch
instructions. The only exceptiona are again branch-relative-on-count, as
it modifies a counter as part of the instruction, as well as any of the
load instructions that are affected.</content>
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<div xmlns='http://www.w3.org/1999/xhtml'>
<pre>
This PR instruments the optimization passes in the SystemZ backend with
calls to `MachineFunction::substituteDebugValuesForInst` where
instruction substitutions are made to instructions that may compute
tracked values.

Tests are also added for each of the substitutions that were inserted.
Details on the individual passes follow.

### systemz-copy-physregs
When a copy targets an access register, we redirect the copy via an
auxiliary register. This leads to the final result being written by a
newly inserted SAR instruction, rather than the original MI, so we need
to update the debug value tracking to account for this.

### systemz-long-branch
This pass relaxes relative branch instructions based on the actual
locations of blocks. Only one of the branch instructions qualifies for
debug value tracking: BRCT, i.e. branch-relative-on-count, which
subtracts 1 from a register and branches if the result is not zero. This
is relaxed into an add-immediate and a conditional branch, so any
`debug-instr-number` present must move to the add-immediate instruction.

### systemz-post-rewrite
This pass replaces `LOCRMux` and `SELRMux` pseudoinstructions with
either the real versions of those instructions, or with branching
programs that implement the intent of the Pseudo. In all these cases,
any `debug-instr-number` attached to the pseudo needs to be reallocated
to the appropriate instruction in the result, either LOCR, SELR, or a
COPY.

### systemz-elim-compare
Similar to systemz-long-branch, for this pass, only few substitutions
are necessary, since it mainly deals with conditional branch
instructions. The only exceptiona are again branch-relative-on-count, as
it modifies a counter as part of the instruction, as well as any of the
load instructions that are affected.</pre>
</div>
</content>
</entry>
<entry>
<title>[Target] Use range-based for loops (NFC) (#98705)</title>
<updated>2024-07-14T00:40:51+00:00</updated>
<author>
<name>Kazu Hirata</name>
<email>kazu@google.com</email>
</author>
<published>2024-07-14T00:40:51+00:00</published>
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<id>5e22a536981483d8411266dccee2ff3e5f31f4a1</id>
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</content>
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<pre>
</pre>
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</entry>
<entry>
<title>[CodeGen] Make the parameter TRI required in some functions. (#85968)</title>
<updated>2024-04-24T13:24:14+00:00</updated>
<author>
<name>Xu Zhang</name>
<email>simonzgx@gmail.com</email>
</author>
<published>2024-04-24T13:24:14+00:00</published>
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<id>f6d431f208c0fa48827eac40e7acf788346a9967</id>
<content type='text'>
Fixes #82659

There are some functions, such as `findRegisterDefOperandIdx` and  `findRegisterDefOperand`, that have too many default parameters. As a result, we have encountered some issues due to the lack of TRI  parameters, as shown in issue #82411.

Following @RKSimon 's suggestion, this patch refactors 9 functions, including `{reads, kills, defines, modifies}Register`,  `registerDefIsDead`, and `findRegister{UseOperandIdx, UseOperand, DefOperandIdx, DefOperand}`, adjusting the order of the TRI parameter and making it required. In addition, all the places that call these functions have also been updated correctly to ensure no additional impact.

After this, the caller of these functions should explicitly know whether to pass the `TargetRegisterInfo` or just a `nullptr`.</content>
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<pre>
Fixes #82659

There are some functions, such as `findRegisterDefOperandIdx` and  `findRegisterDefOperand`, that have too many default parameters. As a result, we have encountered some issues due to the lack of TRI  parameters, as shown in issue #82411.

Following @RKSimon 's suggestion, this patch refactors 9 functions, including `{reads, kills, defines, modifies}Register`,  `registerDefIsDead`, and `findRegister{UseOperandIdx, UseOperand, DefOperandIdx, DefOperand}`, adjusting the order of the TRI parameter and making it required. In addition, all the places that call these functions have also been updated correctly to ensure no additional impact.

After this, the caller of these functions should explicitly know whether to pass the `TargetRegisterInfo` or just a `nullptr`.</pre>
</div>
</content>
</entry>
<entry>
<title>Reapply "Convert many LivePhysRegs uses to LiveRegUnits" (#84338)</title>
<updated>2024-03-08T13:35:00+00:00</updated>
<author>
<name>AtariDreams</name>
<email>83477269+AtariDreams@users.noreply.github.com</email>
</author>
<published>2024-03-08T13:35:00+00:00</published>
<link rel='alternate' type='text/html' href='https://git.belthelziquor.com/llvm-project.git/commit/?id=7c21495fee927359d642793d2eeb24696a301262'/>
<id>7c21495fee927359d642793d2eeb24696a301262</id>
<content type='text'>
This only converts the instances where all that is needed is to change
the variable type name.

Basically, anything that involves a function that LiveRegUnits does not
directly have was skipped to play it safe.

Reverts
https://github.com/llvm/llvm-project/commit/7a0e222a17058a311b69153d0b6f1b4459414778</content>
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<pre>
This only converts the instances where all that is needed is to change
the variable type name.

Basically, anything that involves a function that LiveRegUnits does not
directly have was skipped to play it safe.

Reverts
https://github.com/llvm/llvm-project/commit/7a0e222a17058a311b69153d0b6f1b4459414778</pre>
</div>
</content>
</entry>
<entry>
<title>Revert "Convert many LivePhysRegs uses to LiveRegUnits (#83905)"</title>
<updated>2024-03-07T08:20:26+00:00</updated>
<author>
<name>Jay Foad</name>
<email>jay.foad@amd.com</email>
</author>
<published>2024-03-07T08:16:52+00:00</published>
<link rel='alternate' type='text/html' href='https://git.belthelziquor.com/llvm-project.git/commit/?id=7a0e222a17058a311b69153d0b6f1b4459414778'/>
<id>7a0e222a17058a311b69153d0b6f1b4459414778</id>
<content type='text'>
This reverts commit 2a13422b8bcee449405e3ebff957b4020805f91c.

It was causing test failures on the expensive check builders.
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<pre>
This reverts commit 2a13422b8bcee449405e3ebff957b4020805f91c.

It was causing test failures on the expensive check builders.
</pre>
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</content>
</entry>
<entry>
<title>Convert many LivePhysRegs uses to LiveRegUnits (#83905)</title>
<updated>2024-03-06T05:08:14+00:00</updated>
<author>
<name>AtariDreams</name>
<email>83477269+AtariDreams@users.noreply.github.com</email>
</author>
<published>2024-03-06T05:08:14+00:00</published>
<link rel='alternate' type='text/html' href='https://git.belthelziquor.com/llvm-project.git/commit/?id=2a13422b8bcee449405e3ebff957b4020805f91c'/>
<id>2a13422b8bcee449405e3ebff957b4020805f91c</id>
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<pre>
</pre>
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</entry>
<entry>
<title>[SystemZ] Don't use FP Load and Test as comparisons to same reg (#78074)</title>
<updated>2024-01-15T18:36:40+00:00</updated>
<author>
<name>Jonas Paulsson</name>
<email>paulson1@linux.ibm.com</email>
</author>
<published>2024-01-15T18:36:40+00:00</published>
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<id>1d1893097a6319a6402331a54a588b1a5d961808</id>
<content type='text'>
The usage of FP Load and Test instructions as a comparison against zero
with the assumption that the dest reg will always reflect the source reg is
actually incorrect: Unfortunately, a SNaN will be converted to a QNaN, so the
instruction may actually change the value as opposed to being a pure register
move with a test.

This patch
- changes instruction selection to always emit FP LT with a scratch def
  reg, which will typically be allocated to the same reg if dead.
- Removes the conversions into FP LT in SystemZElimcompare.
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<pre>
The usage of FP Load and Test instructions as a comparison against zero
with the assumption that the dest reg will always reflect the source reg is
actually incorrect: Unfortunately, a SNaN will be converted to a QNaN, so the
instruction may actually change the value as opposed to being a pure register
move with a test.

This patch
- changes instruction selection to always emit FP LT with a scratch def
  reg, which will typically be allocated to the same reg if dead.
- Removes the conversions into FP LT in SystemZElimcompare.
</pre>
</div>
</content>
</entry>
<entry>
<title>[SystemZ] Remove unnecessary casts to SystemZInstrInfo (NFC).</title>
<updated>2022-06-20T12:52:06+00:00</updated>
<author>
<name>Jonas Paulsson</name>
<email>paulsson@linux.vnet.ibm.com</email>
</author>
<published>2022-06-20T12:20:03+00:00</published>
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<id>3432d40c7fa4229ab810845c88fabcb8c9b20aa0</id>
<content type='text'>
Review: Ulrich Weigand
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Review: Ulrich Weigand
</pre>
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