the extension enabled with xmipscbop.

Please refer "MIPS RV64 P8700/P8700-F Multiprocessing System
Programmer’s Guide" for more info on the extension at
https://mips.com/wp-content/uploads/2025/06/P8700_Programmers_Reference_Manual_Rev1.84_5-31-2025.pdf

Follow-up to #141333. Relocation generation called both addReloc and
applyFixup, with the default addReloc invoking shouldForceRelocation,
resulting in three virtual calls. This approach was also inflexible, as
targets needing additional data required extending
`shouldForceRelocation` (see #73721, resolved by #141311).

This change integrates relocation handling into applyFixup, eliminating
two virtual calls. The prior default addReloc is renamed to
maybeAddReloc. Targets overriding addReloc now call their customized
addReloc implementation.

Similar to #139872. This patch adds isel patterns to match
`riscv_brcc` and `riscv_selectcc_frag` to XAndesPerf branch
instructions.

For permutation intrinsics, the float data type is not used during
processing. We only need to check whether its plain type is supported,
rather than the float type. This is like what we did in
https://github.com/llvm/llvm-project/blob/651c5208f8597f1f80349f6208e69bf9ea1c2862/llvm/lib/Target/RISCV/RISCVInstrInfoVVLPatterns.td#L2958

Similarly to #146710, for vslide1ups vl only determines the destination
elements written to so we can safely reduce their AVL.

We cannot do this for vslide1downs as the vl determines which lane the
new element is to be inserted in, so some negative tests have been
added.

For vslideup and vslidedown, vl controls the elements which are written
just like other vector instructions. So unless I'm missing something it
should be safe to reduce them. For vslidedown, the specification states
that elements past vl may be read.

We already reduce vslideup and vslidedown in
RISCVVectorPeephole::tryToReduceVL where we just check for
RISCVII::elementsDependOnVL.

Eventually we should replace the whitelist with
RISCVII::elementsDependOnVL once we have test coverage. I've also added
an assert just to double check the instructions we currently support.

This helps reduce vl toggles for fixed-order recurrences vectorized with
EVL tail folding.