llvm-project.git/llvm/lib/Target/RISCV/RISCVTargetTransformInfo.cpp, branch users/ojhunt/ptrauth-additions Unnamed repository; edit this file 'description' to name the repository. [ASan][RISCV] Support asan check for segment load/store RVV intrinsics. (#161317) 2025-10-07T07:05:37+00:00 Hank Chang hank.chang@sifive.com 2025-10-07T07:05:37+00:00 958ec32e7d9c54786df8b874b824a02dea87ef6a RVV segment is an array of `SegNum` contingous elements. This patch emulates RVV segment as a large integer with bitwidth equaled to `SegNum * SEW`. The reason to not emulate RVV segment as some aggregated type is that vector type should use primitive types as element types. There is another approach is to create `SegNum` InterestingMemoryOperand objects. It could avoid create pseudo types, but this approach also generates large code for asan check. Co-authored-by: Yeting Kuo <yeting.kuo@sifive.com> 
RVV segment is an array of `SegNum` contingous elements. This patch
emulates RVV segment as a large integer with bitwidth equaled to `SegNum
* SEW`. The reason to not emulate RVV segment as some aggregated type is
that vector type should use primitive types as element types.
There is another approach is to create `SegNum` InterestingMemoryOperand
objects. It could avoid create pseudo types, but this approach also
generates large code for asan check.

Co-authored-by: Yeting Kuo <yeting.kuo@sifive.com>
 [RISCV] Allow non-canonicalized splats in isProfitableToSinkOperands (#161586) 2025-10-01T21:00:28+00:00 Philip Reames preames@rivosinc.com 2025-10-01T21:00:28+00:00 b389adf56a1610cbdf0aa0a7b0b70b2c6b049f83 This isn't an optimization change - IR transforms should have remove the operands and replaced them with poison. However, I noticed the non-canonical splat structure in a couple of llvm-reduce outputs. This results in us creating extremely atypical IR which is quite misleading about the true cause of what's going on. (Because the non-canonical splat doesn't get sunk, we then prone whatever was actually holding it outside the loop in the original example, eliminating insight as to the true cause of whatever issue we're debugging.) 
This isn't an optimization change - IR transforms should have remove the
operands and replaced them with poison. However, I noticed the
non-canonical splat structure in a couple of llvm-reduce outputs. This
results in us creating extremely atypical IR which is quite misleading
about the true cause of what's going on. (Because the non-canonical
splat doesn't get sunk, we then prone whatever was actually holding it
outside the loop in the original example, eliminating insight as to the
true cause of whatever issue we're debugging.)
 [RISCV] Teach getIntImmCostInst about (X & -(1 << C1) & 0xffffffff) == C2 << C1 (#160163) 2025-09-29T17:36:27+00:00 Craig Topper craig.topper@sifive.com 2025-09-29T17:36:27+00:00 301259a6b1c8146a185e7c1bea46ec02d028243e We can rewrite this to (srai(w)/srli X, C1) == C2 so the AND immediate is free. This transform is done by performSETCCCombine in RISCVISelLowering.cpp. This fixes the opaque constant case mentioned in #157416. 
We can rewrite this to (srai(w)/srli X, C1) == C2 so the AND immediate
is free. This transform is done by performSETCCCombine in
RISCVISelLowering.cpp.

This fixes the opaque constant case mentioned in #157416.
 Revert "[TTI][RISCV] Add cost modelling for intrinsic vp.load.ff (#160470)" 2025-09-27T00:24:56+00:00 ShihPo Hung shihpo.hung@sifive.com 2025-09-27T00:14:17+00:00 2be906b25581eebbd6607a5d99943251617622cb This reverts commit aa08b1a9963f33ded658d3ee655429e1121b5212. 
This reverts commit aa08b1a9963f33ded658d3ee655429e1121b5212.
[ASan][RISCV] Teach AddressSanitizer to support indexed load/store. (#160443) 2025-09-26T19:00:55+00:00 Hank Chang hank.chang@sifive.com 2025-09-26T19:00:55+00:00 d2c189bc739c86bea28e9d603f8973f68869a772 This patch is based on https://github.com/llvm/llvm-project/pull/159713 This patch extends AddressSanitizer to support indexed/segment instructions in RVV. It enables proper instrumentation for these memory operations. A new member, `MaybeOffset`, is added to `InterestingMemoryOperand` to describe the offset between the base pointer and the actual memory reference address. Co-authored-by: Yeting Kuo <yeting.kuo@sifive.com> 
This patch is based on https://github.com/llvm/llvm-project/pull/159713

This patch extends AddressSanitizer to support indexed/segment
instructions in RVV. It enables proper instrumentation for these memory
operations.

A new member, `MaybeOffset`, is added to `InterestingMemoryOperand` to
describe the offset between the base pointer and the actual memory
reference address.

Co-authored-by: Yeting Kuo <yeting.kuo@sifive.com>
 [TTI][RISCV] Add cost modelling for intrinsic vp.load.ff (#160470) 2025-09-26T08:47:10+00:00 Shih-Po Hung shihpo.hung@sifive.com 2025-09-26T08:47:10+00:00 aa08b1a9963f33ded658d3ee655429e1121b5212 Split out from #151300 to isolate TargetTransformInfo cost modelling for fault-only-first loads from VPlan implementation details. This change adds costing support for vp.load.ff independently of the VPlan work. For now, model a vp.load.ff as cost-equivalent to a vp.load. 
Split out from #151300 to isolate TargetTransformInfo cost modelling for
fault-only-first loads from VPlan implementation details. This change
adds costing support for vp.load.ff independently of the VPlan work.

For now, model a vp.load.ff as cost-equivalent to a vp.load.
 [TTI][ASan][RISCV] reland Move InterestingMemoryOperand to Analysis and embed in MemIntrinsicInfo #157863 (#159713) 2025-09-23T01:42:58+00:00 Hank Chang hank.chang@sifive.com 2025-09-23T01:42:58+00:00 f8e51df8e57736d27587baaa5f56e532dfc6de26 [Previously reverted due to failures on asan-rvv-intrinsics.ll, the test case is riscv only and it is triggered by other target] Reland [#157863](https://github.com/llvm/llvm-project/pull/157863), and add `; REQUIRES: riscv-registered-target` in test case to skip the configuration that doesn't register riscv target. Previously asan considers target intrinsics as black boxes, so asan could not instrument accurate check. This patch make SmallVector<InterestingMemoryOperand> a member of MemIntrinsicInfo so that TTI can make targets describe their intrinsic informations to asan. Note, 1. This patch move InterestingMemoryOperand from Transforms to Analysis. 2. Extend MemIntrinsicInfo by adding a SmallVector<InterestingMemoryOperand> member. 3. This patch does not support RVV indexed/segment load/store. 
[Previously reverted due to failures on asan-rvv-intrinsics.ll, the test
case is riscv only and it is triggered by other target]
Reland [#157863](https://github.com/llvm/llvm-project/pull/157863), and
add `; REQUIRES: riscv-registered-target` in test case to skip the
configuration that doesn't register riscv target.


Previously asan considers target intrinsics as black boxes, so asan
could not instrument accurate check. This patch make
SmallVector<InterestingMemoryOperand> a member of MemIntrinsicInfo so
that TTI can make targets describe their intrinsic informations to asan.

Note,
1. This patch move InterestingMemoryOperand from Transforms to Analysis.
2. Extend MemIntrinsicInfo by adding a
SmallVector<InterestingMemoryOperand> member.
3. This patch does not support RVV indexed/segment load/store.
 Revert "[TTI][ASan][RISCV] Move InterestingMemoryOperand to Analysis and embed in MemIntrinsicInfo" (#159700) 2025-09-19T04:13:04+00:00 Florian Mayer fmayer@google.com 2025-09-19T04:13:04+00:00 48f804d609b38f22307f2e1c1345d1e4054cb2c6 Reverts llvm/llvm-project#157863 
Reverts llvm/llvm-project#157863
 [TTI][ASan][RISCV] Move InterestingMemoryOperand to Analysis and embed in MemIntrinsicInfo (#157863) 2025-09-19T03:09:41+00:00 Hank Chang hank.chang@sifive.com 2025-09-19T03:09:41+00:00 f8b7f64ad2d94bbda169023f933f18b31c9b4492 Previously asan considers target intrinsics as black boxes, so asan could not instrument accurate check. This patch make SmallVector<InterestingMemoryOperand> a member of MemIntrinsicInfo so that TTI can make targets describe their intrinsic informations to asan. Note, 1. This patch move InterestingMemoryOperand from Transforms to Analysis. 2. Extend MemIntrinsicInfo by adding a SmallVector<InterestingMemoryOperand> member. 3. This patch does not support RVV indexed/segment load/store. 
Previously asan considers target intrinsics as black boxes, so asan
could not instrument accurate check. This patch make
SmallVector<InterestingMemoryOperand> a member of MemIntrinsicInfo so
that TTI can make targets describe their intrinsic informations to asan.

Note,
1. This patch move InterestingMemoryOperand from Transforms to Analysis.
2. Extend MemIntrinsicInfo by adding a
SmallVector<InterestingMemoryOperand> member.
3. This patch does not support RVV indexed/segment load/store.
 [RISCV] Use hasCPOPLike in isCtpopFast and getPopcntSupport (#158371) 2025-09-12T22:29:44+00:00 Craig Topper craig.topper@sifive.com 2025-09-12T22:29:44+00:00 1131e44ed3f5fadb2d22ff155d4e47f69757d02f