llvm-project.git/llvm/lib/Target/RISCV/RISCVMachineFunctionInfo.cpp, branch users/meinersbur/flang_runtime_split-headers Unnamed repository; edit this file 'description' to name the repository. [RISCV] Add stack clash protection (#117612) 2024-12-10T16:48:26+00:00 Raphael Moreira Zinsly rzinsly@ventanamicro.com 2024-12-10T16:48:26+00:00 708a478d6739aea20a8834cea45490f05b07ca10 Enable `-fstack-clash-protection` for RISCV and stack probe for function prologues. We probe the stack by creating a loop that allocates and probe the stack in ProbeSize chunks. We emit an unrolled probe loop for small allocations and emit a variable length probe loop for bigger ones. 
Enable `-fstack-clash-protection` for RISCV and stack probe for function
prologues.
We probe the stack by creating a loop that allocates and probe the stack
in ProbeSize chunks.
We emit an unrolled probe loop for small allocations and emit a variable
length probe loop for bigger ones.
 [RISCV] Replace RISCV -> RISC-V in comments. NFC 2023-03-27T16:50:17+00:00 Craig Topper craig.topper@sifive.com 2023-03-27T16:15:53+00:00 29463612d21b7d630476fcecdc8301ddf5634bf7 To be consistent with RISC-V branding guidelines https://riscv.org/about/risc-v-branding-guidelines/ Think we should be using RISC-V where possible. More patches will follow. Reviewed By: asb Differential Revision: https://reviews.llvm.org/D146449 
To be consistent with RISC-V branding guidelines
https://riscv.org/about/risc-v-branding-guidelines/
Think we should be using RISC-V where possible.

More patches will follow.

Reviewed By: asb

Differential Revision: https://reviews.llvm.org/D146449
[RISCV] Teach SExtWRemoval to recognize sign extended values that come from arguments. 2022-10-04T22:39:10+00:00 Craig Topper craig.topper@sifive.com 2022-10-04T22:19:49+00:00 ece4bb5ab8941438e4ee0491b59f6d7be77dfec5 This information is not preserved in MIR today. So this patch adds information to RISCVMachineFunctionInfo when the vreg is created for the argument. Reviewed By: reames Differential Revision: https://reviews.llvm.org/D134621 
This information is not preserved in MIR today. So this patch adds
information to RISCVMachineFunctionInfo when the vreg is created for
the argument.

Reviewed By: reames

Differential Revision: https://reviews.llvm.org/D134621
llvm-reduce: Add cloning of target MachineFunctionInfo 2022-06-07T14:14:48+00:00 Matt Arsenault Matthew.Arsenault@amd.com 2022-04-16T02:35:53+00:00 cc5a1b3dd9039d50f6b9caa679d60398f0cec65f MIR support is totally unusable for AMDGPU without this, since the set of reserved registers is set from fields here. Add a clone method to MachineFunctionInfo. This is a subtle variant of the copy constructor that is required if there are any MIR constructs that use pointers. Specifically, at minimum fields that reference MachineBasicBlocks or the MachineFunction need to be adjusted to the values in the new function. 
MIR support is totally unusable for AMDGPU without this, since the set
of reserved registers is set from fields here.

Add a clone method to MachineFunctionInfo. This is a subtle variant of
the copy constructor that is required if there are any MIR constructs
that use pointers. Specifically, at minimum fields that reference
MachineBasicBlocks or the MachineFunction need to be adjusted to the
values in the new function.
[RISCV] Store/restore RISCVMachineFunctionInfo into MIR YAML file 2022-04-08T03:55:48+00:00 Kito Cheng kito.cheng@sifive.com 2022-04-06T01:41:57+00:00 690085c9b715af720ecbd1c009731ba5478cf493 RISCVMachineFunctionInfo has some fields like VarArgsFrameIndex and VarArgsSaveSize are calculated at ISel lowering stage, those info are not contained in MIR files, that cause test cases rely on those field can't not reproduce correctly by MIR dump files. This patch adding the MIR read/write for those fields. Reviewed By: frasercrmck Differential Revision: https://reviews.llvm.org/D123178 
RISCVMachineFunctionInfo has some fields like VarArgsFrameIndex and
VarArgsSaveSize are calculated at ISel lowering stage, those info are
not contained in MIR files, that cause test cases rely on those field
can't not reproduce correctly by MIR dump files.

This patch adding the MIR read/write for those fields.

Reviewed By: frasercrmck

Differential Revision: https://reviews.llvm.org/D123178