the extension enabled with xmipscbop. Please refer "MIPS RV64 P8700/P8700-F Multiprocessing System Programmer’s Guide" for more info on the extension at https://mips.com/wp-content/uploads/2025/06/P8700_Programmers_Reference_Manual_Rev1.84_5-31-2025.pdf
Similar to #139872. This patch adds isel patterns to match `riscv_brcc` and `riscv_selectcc_frag` to XAndesPerf branch instructions.
This is used multiple times in the function.
This adds nds.bfos and nds.bfoz, which are also supported by Andes 45-series CPUs for short forward branch optimization.
This wasn't scalable and made the RISCVCC enum effectively just
a different way of spelling the branch opcodes.
This patch reduces RISCVCC back down to 6 enum values. The primary user
is select pseudoinstructions which now share the same encoding across
all
vendor extensions. The select opcode and condition code are used to
determine the branch opcode when expanding the pseudo.
The Cond SmallVector returned by analyzeBranch now returns the opcode
instead of the RISCVCC. reverseBranchCondition now works directly on
opcodes. getOppositeBranchCondition is also retained.
Stacked on #145622
We don't support any of the immediate branches in this function yet so explicitly exclude them rather than relying on isReg to return false. Remove use of AnalyzeBranch. It doesn't help us much. Part of the code was already getting the operands directly and it just complicated creating a new branch. I also inlined the modifyBranch function so we could use addReg on BuildMI.
As far as I know binutils does not have a similar option and I don't know of a reason we shouldn't accept the RVC hint instructions. The wording in the spec in the past suggested that maybe these weren't valid instruction names, but that's been modified recently.
We were incorrectly changing -1 to 0 for unsigned compares in case 1. The comment incorrectly said UINT64_MAX is bigger than INT64_MAX, but we were doing a signed compare and UINT64_MAX is smaller than INT64_MAX in signed space. Prevent changing 0 constants since we can use x0. The test cases for these are contrived to use addi rd, x0, 0. We're more likely to have a COPY from x0 which we already don't optimize for other reasons. Check if registers are virtual before calling hasOneUse. The use count for physical registers is meaningless.
As of 20b5728b7b1ccc4509a316efb270d46cc9526d69, C always enables Zca, so the check `C || Zca` is equivalent to just checking for `Zca`. This replaces any uses of `HasStdExtCOrZca` with a new `HasStdExtZca` (with the same assembler description, to avoid changes in error messages), and simplifies everywhere where C++ needed to check for either C or Zca. The Subtarget function is just deprecated for the moment.