llvm-project.git/llvm/lib/Target/RISCV/RISCVISelLowering.cpp, branch users/nico/python-2

[RISCV] Added the MIPS prefetch extensions for MIPS RV64 P8700. (#145647)

2025-07-03T08:59:10+00:00

the extension enabled with xmipscbop.

Please refer "MIPS RV64 P8700/P8700-F Multiprocessing System
Programmer’s Guide" for more info on the extension at
https://mips.com/wp-content/uploads/2025/06/P8700_Programmers_Reference_Manual_Rev1.84_5-31-2025.pdf

[RISCV] Add isel patterns for generating XAndesPerf branch immediate instructions (#145147)

2025-07-03T04:47:53+00:00

Similar to #139872. This patch adds isel patterns to match
`riscv_brcc` and `riscv_selectcc_frag` to XAndesPerf branch
instructions.

[DAG] visitFREEZE - always allow freezing multiple operands (#145939)

2025-07-02T10:28:37+00:00

Always try to fold freeze(op(....)) -> op(freeze(),freeze(),freeze(),...).

This patch proposes we drop the opt-in limit for opcodes that are allowed to push a freeze through the op to freeze all its operands, through the tree towards the roots.

I'm struggling to find a strong reason for this limit apart from the DAG freeze handling being immature for so long - as we've improved coverage in canCreateUndefOrPoison/isGuaranteedNotToBeUndefOrPoison it looks like the regressions are not as severe.

Hopefully this will help some of the regression issues in #143102 etc.

[ISel/RISCV] Fix fixed-vector [l]lrint lowering (#145898)

2025-06-30T12:44:34+00:00

Make the fixed-vector lowering of ISD::[L]LRINT use the custom-lowering
routine, lowerVectorXRINT, and fix issues in lowerVectorXRINT related to
this new functionality.

[ISel/RISCV] Refactor isPromotedOpNeedingSplit (NFC) (#146059)

2025-06-28T10:41:26+00:00

[ISel/RISCV] Improve code in lowerFCOPYSIGN (NFC) (#146061)

2025-06-27T16:02:38+00:00

[RISCV] Simplify the check for when to call EmitLoweredCascadedSelect. NFC (#145930)

2025-06-27T15:56:49+00:00

Based on the comments and tests, we only want to call
EmitLoweredCascadedSelect on selects of FP registers.

Everytime we add a new branch with immediate opcode, we've been
excluding it here.

This patch switches to checking that the comparison operands are both
registers so branch on immediate is automatically excluded.

[RISCV] Add ISel patterns for Qualcomm uC Xqcicm extension (#145643)

2025-06-27T06:55:48+00:00

Add codegen patterns for the conditional move instructions in this
extension

[RISCV] Remove separate immediate condition codes from RISCVCC. NFC (#145762)

2025-06-26T06:09:24+00:00

This wasn't scalable and made the RISCVCC enum effectively just
a different way of spelling the branch opcodes.
    
This patch reduces RISCVCC back down to 6 enum values. The primary user
is select pseudoinstructions which now share the same encoding across
all
vendor extensions. The select opcode and condition code are used to
determine the branch opcode when expanding the pseudo.
    
The Cond SmallVector returned by analyzeBranch now returns the opcode
instead of the RISCVCC. reverseBranchCondition now works directly on
opcodes. getOppositeBranchCondition is also retained.

Stacked on #145622

[RISCV] Support fixed vector vp.reverse/splice with Zvfhmin/Zvfbfmin. (#145596)

2025-06-25T20:47:00+00:00

Fix the names of some tests I accidentally misspelled.