llvm-project.git/llvm/lib/Target/RISCV/RISCVISelLowering.cpp, branch users/mingmingl-llvm/samplefdo-profile-format

[RISCV] Add helper method for detecting BEXTI or TH_TST is supported. NFC (#157915)

2025-09-10T19:16:46+00:00

These instructions both extract single bit to bit 0 and fill the upper
bits with 0.

There's at least one place where we check for BEXTI but not TH_TST. I
wanted to keep this patch NFC so that will be a follow up fix.

[RISCV] Extend zvqdot matching to handle disjoint or (#157901)

2025-09-10T17:27:51+00:00

This patch makes use of pattern matching to handle disjoint or. Also, it
simplifies the multiplication matching.

[RISCV] Add helper method for checking for Zicond or XVentanaCondOps. NFC (#157891)

2025-09-10T17:24:47+00:00

These two extensions have identical functionality so we always want to
treat them the same.

[RISCV] Fold (X & -(1 << C1) & 0xffffffff) == C2 << C1 to sraiw X, C1 == C2. (#157617)

2025-09-10T15:51:47+00:00

We had an existing fold for (X & -(1 << C1) & 0xffffffff) == 0
which we can generalize to support comparing to constants other
than 0.
    
Previously we used srliw, but this generalizes better using sraiw.
I'm restricting to the case where C2 is simm12 or 2048 to allow
sraiw+addi/xori+seqz/snez to be used. Other constants require a
more careful analysis of the constants involved.

[RISCV][NFC] Fix a misnamed variable (#157686)

2025-09-10T07:09:23+00:00

[RISCV] Add VendorXTHeadCondMov to useInversedSetcc. (#157758)

2025-09-10T05:47:51+00:00

These instructions have a eqz/nez operand like Zicond and
XVentanaCondOps so the goal of using bexti seems applicable to them as
well.

[RISCV] Undo fneg (fmul x, y) -> fmul x, (fneg y) transform (#157388)

2025-09-09T01:30:33+00:00

InstCombine will hoist an fneg through an fmul, but not for fadd/fsub.
This prevents us from matching fmsub and fnmadd in some cases.

This patch adds a DAG combine to undo this in InstCombine, which helps
some hot loops in 508.namd_r:

@@ -983,18 +983,15 @@
        fld     ft2, 48(a5)
        fld     ft3, 64(a5)
        fld     ft4, 72(a5)
-       fneg.d  fa0, fa0
-       fneg.d  ft0, ft0
-       fneg.d  ft2, ft2
        fmul.d  fa3, ft5, fa3
        fmul.d  fa0, fa3, fa0
        fmul.d  ft0, fa3, ft0
        fmul.d  fa3, fa3, ft2
        fld     ft2, 0(s1)
        fmul.d  fa4, ft5, fa4
-       fmadd.d fa2, fa4, fa2, fa0
-       fmadd.d ft6, fa4, ft6, ft0
-       fmadd.d fa4, fa4, ft1, fa3
+       fmsub.d fa2, fa4, fa2, fa0
+       fmsub.d ft6, fa4, ft6, ft0
+       fmsub.d fa4, fa4, ft1, fa3

This gives a [1.77% improvement in both instruction count and runtime on
508.namd_r](https://lnt.lukelau.me/db_default/v4/nts/profile/1/1022/1021)

This also causes some more fnegs to be sunk after a bitcast to integer,
so they're now done as xor. From glancing at some of the schedules for
WriteFSGN my guess is that this is also profitable.

[RISCV] Allow constants in tryFoldSelectIntoOp (#157376)

2025-09-08T20:11:34+00:00

For simm12 constants this allows the use of e.g. addi/xori, and for
non-simm12 constants seems to still produce better code than the default
lowering.

[RISCV] Check for legal type before calling getSimpleValueType() in matchSplatAsGather. (#157188)

2025-09-06T05:00:38+00:00

This just reorders existing so we do the legal type check first.

In this particular test case we're also protected by the i1 check that I
also moved earlier.

Fixes #157177.

[RISCV] Use non-VP select in gather->strided load combine. NFCish (#157070)

2025-09-06T03:45:48+00:00

Similar to #157068, remove our reliance on trivial VP intrinsics by
using a regular select instruction and letting RISCVVLOptimizer take
care of VL.