These instructions both extract single bit to bit 0 and fill the upper bits with 0. There's at least one place where we check for BEXTI but not TH_TST. I wanted to keep this patch NFC so that will be a follow up fix.
If we don't fold all uses, we end up with an LUI that is used by an ADDI and some loads/stores. This requires the LUI to write a different register than the ADDI or the load/stores uses have to be scheduled between the LUI and ADDI. It prevents macrofusion of the LUI+ADDI on CPUs that support it. It prevents the use of PseudoMovAddr which prevents the LUI+ADDI from being rematerializable. This is based on a patch we have had in our downstream for a while that we originally wrote because of macrofusion and rematerialization. I no longer have any relevant performance or code size numbers for it. --------- Co-authored-by: Jesse Huang <jesse.huang@sifive.com> Co-authored-by: Luke Lau <luke_lau@icloud.com>
These instructions are being used by the scalar efficiency SIG to determine if we should have a standard instruction. Improving our support for these instructions may give better data for their analysis. I'll follow up by adding this to RISCVOptWInstrs too which will remove the 'w' suffixes added here.
Before this patch, the selection for `QC_INSB` and `QC_INSBI` entirely happens in C++, and does not support more than one non-constant input. This patch seeks to rectify this shortcoming, by moving the C++ into a target-specific DAGCombine, and adding `RISCV::QC_INSB`. One advantage is this simplifies the code for handling `QC_INSBI`, as the C++ no longer needs to choose between the two instructions based on the inserted value (this is still done, but via ISel Patterns). Another advantage of the DAGCombine is that this introduction can also shift the inserted value to the `QC_INSB`, which our patterns need (and were previously doing to the constant), and this shift can be CSE'd/optimised with any prior shifts, if they exist. This allows the inserted value to be variable, rather than a constant.
Generate QC_INSB/QC_INSBI from `or (and X, MaskImm), OrImm` iff the value being inserted only sets known zero bits. This is based on a similar DAG to DAG transform done in `AArch64`.
This keeps everything in APInt and makes it easier to understand and maintain.
Fixes #154125.
This patch adds CodeGen support for qc.insbi and qc.insb instructions defined in the Qualcomm uC Xqcibm extension. qc.insbi and qc.insb inserts bits into destination register from immediate and register operand respectively. A sequence of `xor`, `and` & `xor` depending on appropriate conditions are converted to `qc.insbi` or `qc.insb` which depends on the immediate's value.
Reverted the https://github.com/llvm/llvm-project/pull/148779 changes and - handled the uimm9 offset in eliminateFrameIndex () - updated the testcase.