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<title>llvm-project.git/llvm/lib/Target/PowerPC/PPCVSXSwapRemoval.cpp, branch users/nico/python-2</title>
<subtitle>Unnamed repository; edit this file 'description' to name the repository.
</subtitle>
<link rel='alternate' type='text/html' href='https://git.belthelziquor.com/llvm-project.git/'/>
<entry>
<title>[NFC][LLVM][PowerPC] Cleanup pass initialization for PowerPC (#134422)</title>
<updated>2025-04-14T16:18:39+00:00</updated>
<author>
<name>Rahul Joshi</name>
<email>rjoshi@nvidia.com</email>
</author>
<published>2025-04-14T16:18:39+00:00</published>
<link rel='alternate' type='text/html' href='https://git.belthelziquor.com/llvm-project.git/commit/?id=fef5b6f9530c52d623f4729900855e626d5ee722'/>
<id>fef5b6f9530c52d623f4729900855e626d5ee722</id>
<content type='text'>
- Remove calls to pass initialization from pass constructors.
- https://github.com/llvm/llvm-project/issues/111767</content>
<content type='xhtml'>
<div xmlns='http://www.w3.org/1999/xhtml'>
<pre>
- Remove calls to pass initialization from pass constructors.
- https://github.com/llvm/llvm-project/issues/111767</pre>
</div>
</content>
</entry>
<entry>
<title>Revert "[CodeGen] Remove static member function Register::isVirtualRegister. NFC (#127968)"</title>
<updated>2025-02-20T22:06:21+00:00</updated>
<author>
<name>Christopher Di Bella</name>
<email>cjdb@google.com</email>
</author>
<published>2025-02-20T22:02:22+00:00</published>
<link rel='alternate' type='text/html' href='https://git.belthelziquor.com/llvm-project.git/commit/?id=08c69b2ef6eeba19956ad24fb7e9d29e9778cbaa'/>
<id>08c69b2ef6eeba19956ad24fb7e9d29e9778cbaa</id>
<content type='text'>
This reverts commit ff99af7ea03b3be46bec7203bd2b74048d29a52a.
</content>
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<pre>
This reverts commit ff99af7ea03b3be46bec7203bd2b74048d29a52a.
</pre>
</div>
</content>
</entry>
<entry>
<title>[CodeGen] Remove static member function Register::isVirtualRegister. NFC (#127968)</title>
<updated>2025-02-20T16:35:50+00:00</updated>
<author>
<name>Craig Topper</name>
<email>craig.topper@sifive.com</email>
</author>
<published>2025-02-20T16:35:50+00:00</published>
<link rel='alternate' type='text/html' href='https://git.belthelziquor.com/llvm-project.git/commit/?id=ff99af7ea03b3be46bec7203bd2b74048d29a52a'/>
<id>ff99af7ea03b3be46bec7203bd2b74048d29a52a</id>
<content type='text'>
Use nonstatic member instead. This requires explicit conversions, but
many will go away as we continue converting unsigned to Register.

In a few places where it was simple, I changed unsigned to Register.</content>
<content type='xhtml'>
<div xmlns='http://www.w3.org/1999/xhtml'>
<pre>
Use nonstatic member instead. This requires explicit conversions, but
many will go away as we continue converting unsigned to Register.

In a few places where it was simple, I changed unsigned to Register.</pre>
</div>
</content>
</entry>
<entry>
<title>[PowerPC] Remove unused includes (NFC) (#116163)</title>
<updated>2024-11-14T15:55:18+00:00</updated>
<author>
<name>Kazu Hirata</name>
<email>kazu@google.com</email>
</author>
<published>2024-11-14T15:55:18+00:00</published>
<link rel='alternate' type='text/html' href='https://git.belthelziquor.com/llvm-project.git/commit/?id=f71cb9dbb739bb58ce7e52e49fe384ff2ff11687'/>
<id>f71cb9dbb739bb58ce7e52e49fe384ff2ff11687</id>
<content type='text'>
Identified with misc-include-cleaner.</content>
<content type='xhtml'>
<div xmlns='http://www.w3.org/1999/xhtml'>
<pre>
Identified with misc-include-cleaner.</pre>
</div>
</content>
</entry>
<entry>
<title>[llvm] Use *{Map,Set}::contains (NFC)</title>
<updated>2023-03-16T01:06:32+00:00</updated>
<author>
<name>Kazu Hirata</name>
<email>kazu@google.com</email>
</author>
<published>2023-03-16T01:06:32+00:00</published>
<link rel='alternate' type='text/html' href='https://git.belthelziquor.com/llvm-project.git/commit/?id=398af9b43bbfbff291faac5bce524eca675d6caf'/>
<id>398af9b43bbfbff291faac5bce524eca675d6caf</id>
<content type='text'>
</content>
<content type='xhtml'>
<div xmlns='http://www.w3.org/1999/xhtml'>
<pre>
</pre>
</div>
</content>
</entry>
<entry>
<title>[CodeGen][Target] Remove uses of Register::isPhysicalRegister/isVirtualRegister. NFC</title>
<updated>2023-01-14T07:12:48+00:00</updated>
<author>
<name>Craig Topper</name>
<email>craig.topper@sifive.com</email>
</author>
<published>2023-01-14T06:57:36+00:00</published>
<link rel='alternate' type='text/html' href='https://git.belthelziquor.com/llvm-project.git/commit/?id=79858d1908b53560941b7d8f4d98e5ac781c674b'/>
<id>79858d1908b53560941b7d8f4d98e5ac781c674b</id>
<content type='text'>
Use isPhysical/isVirtual methods.
</content>
<content type='xhtml'>
<div xmlns='http://www.w3.org/1999/xhtml'>
<pre>
Use isPhysical/isVirtual methods.
</pre>
</div>
</content>
</entry>
<entry>
<title>[PowerPC] Fix PPCVSXSwapRemoval pass to include MTVSCR and MFVSCR as not swappable.</title>
<updated>2022-06-17T15:14:24+00:00</updated>
<author>
<name>Quinn Pham</name>
<email>Quinn.Pham@ibm.com</email>
</author>
<published>2022-06-17T14:33:32+00:00</published>
<link rel='alternate' type='text/html' href='https://git.belthelziquor.com/llvm-project.git/commit/?id=deb7655209a7d74257b651ade97bfc63043174ec'/>
<id>deb7655209a7d74257b651ade97bfc63043174ec</id>
<content type='text'>
This patch adds the instructions `MTVSCR` and `MFVSCR` as not swappable to the
PPCVSXSwapRemoval pass because they are not lane-insensitive. This will prevent
the compiler from optimizing out required swaps when using `lxvd2x` and
`stxvd2x`.

Reviewed By: #powerpc, nemanjai

Differential Revision: https://reviews.llvm.org/D128062
</content>
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<div xmlns='http://www.w3.org/1999/xhtml'>
<pre>
This patch adds the instructions `MTVSCR` and `MFVSCR` as not swappable to the
PPCVSXSwapRemoval pass because they are not lane-insensitive. This will prevent
the compiler from optimizing out required swaps when using `lxvd2x` and
`stxvd2x`.

Reviewed By: #powerpc, nemanjai

Differential Revision: https://reviews.llvm.org/D128062
</pre>
</div>
</content>
</entry>
<entry>
<title>[PowerPC] Provide patterns for permuted scalar to vector for pre-P8</title>
<updated>2020-12-29T12:49:25+00:00</updated>
<author>
<name>Nemanja Ivanovic</name>
<email>nemanja.i.ibm@gmail.com</email>
</author>
<published>2020-12-29T12:32:45+00:00</published>
<link rel='alternate' type='text/html' href='https://git.belthelziquor.com/llvm-project.git/commit/?id=7486de1b2eced2cccc7b0b95598e9ab45039d700'/>
<id>7486de1b2eced2cccc7b0b95598e9ab45039d700</id>
<content type='text'>
We will emit these permuted nodes on all VSX little endian subtargets
but don't have the patterns available to match them on subtargets
that don't have direct moves.

Fixes: https://bugs.llvm.org/show_bug.cgi?id=47916
</content>
<content type='xhtml'>
<div xmlns='http://www.w3.org/1999/xhtml'>
<pre>
We will emit these permuted nodes on all VSX little endian subtargets
but don't have the patterns available to match them on subtargets
that don't have direct moves.

Fixes: https://bugs.llvm.org/show_bug.cgi?id=47916
</pre>
</div>
</content>
</entry>
<entry>
<title>[PowerPC] Don't remove single swap between the load and store</title>
<updated>2020-08-04T15:38:15+00:00</updated>
<author>
<name>Nemanja Ivanovic</name>
<email>nemanja.i.ibm@gmail.com</email>
</author>
<published>2020-08-04T15:37:57+00:00</published>
<link rel='alternate' type='text/html' href='https://git.belthelziquor.com/llvm-project.git/commit/?id=14d726acd6041ee8fc595e48ec871b50b40ccc1d'/>
<id>14d726acd6041ee8fc595e48ec871b50b40ccc1d</id>
<content type='text'>
The swap removal pass looks to remove swaps when a loaded value is swapped, some
number of lane-insensitive operations are performed and then the value is
swapped again and stored.

However, in a situation where we load the value, swap it and then store it
without swapping again, the pass erroneously removes the single swap. The
reason is that both checks in the same equivalence class:

- load feeds a swap
- swap feeds a store

pass. However, there is no check that the two swaps are actually a single swap.
This patch just fixes that.

Differential revision: https://reviews.llvm.org/D84785
</content>
<content type='xhtml'>
<div xmlns='http://www.w3.org/1999/xhtml'>
<pre>
The swap removal pass looks to remove swaps when a loaded value is swapped, some
number of lane-insensitive operations are performed and then the value is
swapped again and stored.

However, in a situation where we load the value, swap it and then store it
without swapping again, the pass erroneously removes the single swap. The
reason is that both checks in the same equivalence class:

- load feeds a swap
- swap feeds a store

pass. However, there is no check that the two swaps are actually a single swap.
This patch just fixes that.

Differential revision: https://reviews.llvm.org/D84785
</pre>
</div>
</content>
</entry>
<entry>
<title>Apply llvm-prefer-register-over-unsigned from clang-tidy to LLVM</title>
<updated>2019-08-15T19:22:08+00:00</updated>
<author>
<name>Daniel Sanders</name>
<email>daniel_l_sanders@apple.com</email>
</author>
<published>2019-08-15T19:22:08+00:00</published>
<link rel='alternate' type='text/html' href='https://git.belthelziquor.com/llvm-project.git/commit/?id=0c476111317cb7aaa9a3e9f75e1c35f83122ee26'/>
<id>0c476111317cb7aaa9a3e9f75e1c35f83122ee26</id>
<content type='text'>
Summary:
This clang-tidy check is looking for unsigned integer variables whose initializer
starts with an implicit cast from llvm::Register and changes the type of the
variable to llvm::Register (dropping the llvm:: where possible).

Partial reverts in:
X86FrameLowering.cpp - Some functions return unsigned and arguably should be MCRegister
X86FixupLEAs.cpp - Some functions return unsigned and arguably should be MCRegister
X86FrameLowering.cpp - Some functions return unsigned and arguably should be MCRegister
HexagonBitSimplify.cpp - Function takes BitTracker::RegisterRef which appears to be unsigned&amp;
MachineVerifier.cpp - Ambiguous operator==() given MCRegister and const Register
PPCFastISel.cpp - No Register::operator-=()
PeepholeOptimizer.cpp - TargetInstrInfo::optimizeLoadInstr() takes an unsigned&amp;
MachineTraceMetrics.cpp - MachineTraceMetrics lacks a suitable constructor

Manual fixups in:
ARMFastISel.cpp - ARMEmitLoad() now takes a Register&amp; instead of unsigned&amp;
HexagonSplitDouble.cpp - Ternary operator was ambiguous between unsigned/Register
HexagonConstExtenders.cpp - Has a local class named Register, used llvm::Register instead of Register.
PPCFastISel.cpp - PPCEmitLoad() now takes a Register&amp; instead of unsigned&amp;

Depends on D65919

Reviewers: arsenm, bogner, craig.topper, RKSimon

Reviewed By: arsenm

Subscribers: RKSimon, craig.topper, lenary, aemerson, wuzish, jholewinski, MatzeB, qcolombet, dschuff, jyknight, dylanmckay, sdardis, nemanjai, jvesely, wdng, nhaehnle, sbc100, jgravelle-google, kristof.beyls, hiraditya, aheejin, kbarton, fedor.sergeev, javed.absar, asb, rbar, johnrusso, simoncook, apazos, sabuasal, niosHD, jrtc27, MaskRay, zzheng, edward-jones, atanasyan, rogfer01, MartinMosbeck, brucehoult, the_o, tpr, PkmX, jocewei, jsji, Petar.Avramovic, asbirlea, Jim, s.egerton, llvm-commits

Tags: #llvm

Differential Revision: https://reviews.llvm.org/D65962

llvm-svn: 369041
</content>
<content type='xhtml'>
<div xmlns='http://www.w3.org/1999/xhtml'>
<pre>
Summary:
This clang-tidy check is looking for unsigned integer variables whose initializer
starts with an implicit cast from llvm::Register and changes the type of the
variable to llvm::Register (dropping the llvm:: where possible).

Partial reverts in:
X86FrameLowering.cpp - Some functions return unsigned and arguably should be MCRegister
X86FixupLEAs.cpp - Some functions return unsigned and arguably should be MCRegister
X86FrameLowering.cpp - Some functions return unsigned and arguably should be MCRegister
HexagonBitSimplify.cpp - Function takes BitTracker::RegisterRef which appears to be unsigned&amp;
MachineVerifier.cpp - Ambiguous operator==() given MCRegister and const Register
PPCFastISel.cpp - No Register::operator-=()
PeepholeOptimizer.cpp - TargetInstrInfo::optimizeLoadInstr() takes an unsigned&amp;
MachineTraceMetrics.cpp - MachineTraceMetrics lacks a suitable constructor

Manual fixups in:
ARMFastISel.cpp - ARMEmitLoad() now takes a Register&amp; instead of unsigned&amp;
HexagonSplitDouble.cpp - Ternary operator was ambiguous between unsigned/Register
HexagonConstExtenders.cpp - Has a local class named Register, used llvm::Register instead of Register.
PPCFastISel.cpp - PPCEmitLoad() now takes a Register&amp; instead of unsigned&amp;

Depends on D65919

Reviewers: arsenm, bogner, craig.topper, RKSimon

Reviewed By: arsenm

Subscribers: RKSimon, craig.topper, lenary, aemerson, wuzish, jholewinski, MatzeB, qcolombet, dschuff, jyknight, dylanmckay, sdardis, nemanjai, jvesely, wdng, nhaehnle, sbc100, jgravelle-google, kristof.beyls, hiraditya, aheejin, kbarton, fedor.sergeev, javed.absar, asb, rbar, johnrusso, simoncook, apazos, sabuasal, niosHD, jrtc27, MaskRay, zzheng, edward-jones, atanasyan, rogfer01, MartinMosbeck, brucehoult, the_o, tpr, PkmX, jocewei, jsji, Petar.Avramovic, asbirlea, Jim, s.egerton, llvm-commits

Tags: #llvm

Differential Revision: https://reviews.llvm.org/D65962

llvm-svn: 369041
</pre>
</div>
</content>
</entry>
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