llvm-project.git/llvm/lib/Target/PowerPC/PPCSubtarget.h, branch users/nico/python-2

[SelectionDAG] Add empty implementation of SelectionDAGInfo to some targets (#119968)

2024-12-16T12:13:46+00:00

#119969 adds a couple of new methods to this class, which will need to
be overridden by these targets.

Part of #119709.

Pull Request: https://github.com/llvm/llvm-project/pull/119968

[NFC][PowerPC] Add getScalarIntVT to return MVT based on arch (#115203)

2024-11-11T17:25:14+00:00

Add `getScalarIntVT()` to return scalar int VT based on if arch is 32 or
64bit.

[PowerPC] Add support for -mcpu=pwr11 / -mtune=pwr11 (#99511)

2024-07-23T13:49:41+00:00

This PR adds support for -mcpu=pwr11/power11 and -mtune=pwr11/power11 in
clang and llvm.

[AIX] Support per global code model. (#79202)

2024-03-15T16:52:04+00:00

Exploit the per global code model attribute on AIX. On AIX we need to
update both the code sequence used to access the global (either 1 or 2
instructions for small and large code model respectively) and the
storage mapping class that we emit the toc entry.

---------

Co-authored-by: Amy Kwan

[AIX][TOC] Fix buildbot failures from commit b4ae8df (#85303)

2024-03-14T20:26:58+00:00

The following tests fail when built with Address
and Undefined sanitizers:
CodeGen/PowerPC/basic-toc-data-def.ll
CodeGen/PowerPC/toc-data-large-array2.ll

Subtarget may be null in emitGlobalVariable, for example in the testcase
where we have no functions in the IR. The fix moves this function from
PPCSubtarget to a static helper function. This only fails with
sanitizers because the Subtarget is not used in the member function.

[AIX][TOC] Add -mtocdata/-mno-tocdata options on AIX (#67999)

2024-03-13T14:26:31+00:00

This patch enables support that the XL compiler had for AIX under
-qdatalocal/-qdataimported.

[AIX][TLS] Generate optimized local-exec access code sequence using X-Form loads/stores

2023-07-06T12:57:05+00:00

This patch is a follow up to D149722, D152669 and D153645, where a slightly more
optimized code sequence is generated for 64-bit and 32-bit local-exec accesses
when optimizations are turned on.

Handling is added PPCISelDAGToDAG.cpp in order to check if any D-form loads or
stores that follow an PPCISD::ADD_TLS can be optimized to use an X-Form load or
store. In this particular situation, this allows the ADD_TLS node to be removed
completely.

Differential Revision: https://reviews.llvm.org/D150367

[MachineCopyPropagation] Eliminate spillage copies that might be caused by eviction chain

2023-02-08T03:34:25+00:00

Remove spill-reload like copy chains. For example
```
r0 = COPY r1
r1 = COPY r2
r2 = COPY r3
r3 = COPY r4

r4 = COPY r3
r3 = COPY r2
r2 = COPY r1
r1 = COPY r0
```
will be folded into
```
r0 = COPY r1
r1 = COPY r4

r4 = COPY r1
r1 = COPY r0
```

Reviewed By: qcolombet

Differential Revision: https://reviews.llvm.org/D122118

[NFC][TargetParser] Remove llvm/ADT/Triple.h

2023-02-07T12:39:46+00:00

I also ran `git clang-format` to get the headers in the right order for
the new location, which has changed the order of other headers in two
files.

[PPC] Add support for tune-cpu attribute

2023-01-06T18:01:48+00:00

clang (like gcc) has the -mtune= command line option. This option
adds the "tune-cpu" attribute to a function. The intended functionality
is that the scheduling model of that cpu is used. E.g. -mtune=pwr9 -march=pwr8
generates only instructions supported on pwr8 but uses the scheduling model
of pwr9 for it.
This PR adds the infrastructure to support this in LLVM.
clang support was added in https://reviews.llvm.org/D130526.

Reviewed By: amyk, qiucf

Differential Revision: https://reviews.llvm.org/D138317