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<title>llvm-project.git/llvm/lib/Target/PowerPC/PPCSubtarget.cpp, branch main</title>
<subtitle>Unnamed repository; edit this file 'description' to name the repository.
</subtitle>
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<entry>
<title>PPC: Split 64bit target feature into 64bit and 64bit-support (#157206)</title>
<updated>2025-09-16T03:43:53+00:00</updated>
<author>
<name>Matt Arsenault</name>
<email>Matthew.Arsenault@amd.com</email>
</author>
<published>2025-09-16T03:43:53+00:00</published>
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<id>e5bbaa9c8fb6e06dbcbd39404039cc5d31df4410</id>
<content type='text'>
This was being used for 2 different purposes.

The TargetMachine constructor prepends +64bit based on isPPC64
triples as a mode switch. The same feature name was also explicitly
added to different processors, making it impossible to perform a pure
feature check for whether 64-bit mode is enabled ir not. i.e.,
checkFeatures("+64bit") would be true even for ppc32 triples.

The comment in tablegen suggests it's relevant to track which processors
support 64-bit mode independently of whether that's the active compile
target, so replace that with a new feature.</content>
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<pre>
This was being used for 2 different purposes.

The TargetMachine constructor prepends +64bit based on isPPC64
triples as a mode switch. The same feature name was also explicitly
added to different processors, making it impossible to perform a pure
feature check for whether 64-bit mode is enabled ir not. i.e.,
checkFeatures("+64bit") would be true even for ppc32 triples.

The comment in tablegen suggests it's relevant to track which processors
support 64-bit mode independently of whether that's the active compile
target, so replace that with a new feature.</pre>
</div>
</content>
</entry>
<entry>
<title>PPC: Use StringRef for subtarget constructor arguments (#157409)</title>
<updated>2025-09-08T10:50:16+00:00</updated>
<author>
<name>Matt Arsenault</name>
<email>Matthew.Arsenault@amd.com</email>
</author>
<published>2025-09-08T10:50:16+00:00</published>
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<id>e1acbc350955b30e581e218145beb39e671234cf</id>
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<pre>
</pre>
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</content>
</entry>
<entry>
<title>PPC: Remove TargetTriple from PPCSubtarget (#157404)</title>
<updated>2025-09-08T10:18:31+00:00</updated>
<author>
<name>Matt Arsenault</name>
<email>Matthew.Arsenault@amd.com</email>
</author>
<published>2025-09-08T10:18:31+00:00</published>
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<id>761b56e08e2258a626604148385b25e8fb4f19b2</id>
<content type='text'>
This already exists in the base class.</content>
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<pre>
This already exists in the base class.</pre>
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</content>
</entry>
<entry>
<title>[MISched] Use SchedRegion in overrideSchedPolicy and overridePostRASchedPolicy (#149297)</title>
<updated>2025-07-22T07:55:12+00:00</updated>
<author>
<name>Harrison Hao</name>
<email>57025411+harrisonGPU@users.noreply.github.com</email>
</author>
<published>2025-07-22T07:55:12+00:00</published>
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<id>8c14d3f44f51be053e91612f4ad2d77bf04b6b3a</id>
<content type='text'>
This patch updates `overrideSchedPolicy` and `overridePostRASchedPolicy`
to take a
`SchedRegion` parameter instead of just `NumRegionInstrs`. This provides
access to both the
instruction range and the parent `MachineBasicBlock`, which enables
looking up function-level
attributes.

With this change, targets can select post-RA scheduling direction per
function using a function
attribute. For example:

```cpp
void overridePostRASchedPolicy(MachineSchedPolicy &amp;Policy,
                               const SchedRegion &amp;Region) const {
  const Function &amp;F = Region.RegionBegin-&gt;getMF()-&gt;getFunction();
  Attribute Attr = F.getFnAttribute("amdgpu-post-ra-direction");
  ...
}</content>
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<div xmlns='http://www.w3.org/1999/xhtml'>
<pre>
This patch updates `overrideSchedPolicy` and `overridePostRASchedPolicy`
to take a
`SchedRegion` parameter instead of just `NumRegionInstrs`. This provides
access to both the
instruction range and the parent `MachineBasicBlock`, which enables
looking up function-level
attributes.

With this change, targets can select post-RA scheduling direction per
function using a function
attribute. For example:

```cpp
void overridePostRASchedPolicy(MachineSchedPolicy &amp;Policy,
                               const SchedRegion &amp;Region) const {
  const Function &amp;F = Region.RegionBegin-&gt;getMF()-&gt;getFunction();
  Attribute Attr = F.getFnAttribute("amdgpu-post-ra-direction");
  ...
}</pre>
</div>
</content>
</entry>
<entry>
<title>[SelectionDAG] Add empty implementation of SelectionDAGInfo to some targets (#119968)</title>
<updated>2024-12-16T12:13:46+00:00</updated>
<author>
<name>Sergei Barannikov</name>
<email>barannikov88@gmail.com</email>
</author>
<published>2024-12-16T12:13:46+00:00</published>
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<id>03847f19f2e462a339e1afa1093f253ec8a23765</id>
<content type='text'>
#119969 adds a couple of new methods to this class, which will need to
be overridden by these targets.

Part of #119709.

Pull Request: https://github.com/llvm/llvm-project/pull/119968
</content>
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<pre>
#119969 adds a couple of new methods to this class, which will need to
be overridden by these targets.

Part of #119709.

Pull Request: https://github.com/llvm/llvm-project/pull/119968
</pre>
</div>
</content>
</entry>
<entry>
<title>[PowerPC] Remove unused includes (NFC) (#116163)</title>
<updated>2024-11-14T15:55:18+00:00</updated>
<author>
<name>Kazu Hirata</name>
<email>kazu@google.com</email>
</author>
<published>2024-11-14T15:55:18+00:00</published>
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<id>f71cb9dbb739bb58ce7e52e49fe384ff2ff11687</id>
<content type='text'>
Identified with misc-include-cleaner.</content>
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<pre>
Identified with misc-include-cleaner.</pre>
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</content>
</entry>
<entry>
<title>[PowerPC][LLC] Utilize PPC::getNormalizedPPCTargetCPU() to set CPU (#113943)</title>
<updated>2024-11-04T14:40:54+00:00</updated>
<author>
<name>zhijian lin</name>
<email>zhijian@ca.ibm.com</email>
</author>
<published>2024-11-04T14:40:54+00:00</published>
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<id>a51712751c184ebe056718c938d2526693a31564</id>
<content type='text'>
Utilize common API in PPCTargetParser
(https://github.com/llvm/llvm-project/pull/97541) to set default CPU
with same interfaces for LLC.
This will update AIX default CPU to pwr7 and LoP powerppc64 default CPU
to ppc64.</content>
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<pre>
Utilize common API in PPCTargetParser
(https://github.com/llvm/llvm-project/pull/97541) to set default CPU
with same interfaces for LLC.
This will update AIX default CPU to pwr7 and LoP powerppc64 default CPU
to ppc64.</pre>
</div>
</content>
</entry>
<entry>
<title>[ARM][Mips][PowerPC] Remove unnecessary static_cast creating GISel InstructionSelector. NFC</title>
<updated>2024-07-10T17:28:32+00:00</updated>
<author>
<name>Craig Topper</name>
<email>craig.topper@sifive.com</email>
</author>
<published>2024-07-10T17:23:11+00:00</published>
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<id>0df714364a731822590b3da54f33ed0d6ddee873</id>
<content type='text'>
Some targets only pass a TargetMachine &amp; to their subtarget constructor
and require a static_cast to their target-specific TargetMachine subclass
to create *InstructionSelector.

These 3 targets already have the correct TargetMachine subclass
reference so no cast is needed.
</content>
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<pre>
Some targets only pass a TargetMachine &amp; to their subtarget constructor
and require a static_cast to their target-specific TargetMachine subclass
to create *InstructionSelector.

These 3 targets already have the correct TargetMachine subclass
reference so no cast is needed.
</pre>
</div>
</content>
</entry>
<entry>
<title>[IR] Don't include Module.h in Analysis.h (NFC) (#97023)</title>
<updated>2024-06-28T12:30:47+00:00</updated>
<author>
<name>Nikita Popov</name>
<email>npopov@redhat.com</email>
</author>
<published>2024-06-28T12:30:47+00:00</published>
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<id>4169338e75cdce73d34063532db598c95ee82ae4</id>
<content type='text'>
Replace it with a forward declaration instead. Analysis.h is pulled in
by all passes, but not all passes need to access the module.</content>
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<pre>
Replace it with a forward declaration instead. Analysis.h is pulled in
by all passes, but not all passes need to access the module.</pre>
</div>
</content>
</entry>
<entry>
<title>[CodeGen] Remove target SubRegLiveness flags (#95437)</title>
<updated>2024-06-14T07:51:56+00:00</updated>
<author>
<name>David Green</name>
<email>david.green@arm.com</email>
</author>
<published>2024-06-14T07:51:56+00:00</published>
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<id>706e1975400b3f30bd406b694bb711a7c7dbe1c4</id>
<content type='text'>
This removes the uses of target flags to disable subreg liveness,
relying on the `-enable-subreg-liveness` flag instead. The
`-enable-subreg-liveness` flag has been changed to take precedence over
the subtarget if set, and one use of `Subtarget-&gt;enableSubRegLiveness()`
has been changed to `MRI-&gt;subRegLivenessEnabled()` to make sure the
option properly applies.</content>
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<pre>
This removes the uses of target flags to disable subreg liveness,
relying on the `-enable-subreg-liveness` flag instead. The
`-enable-subreg-liveness` flag has been changed to take precedence over
the subtarget if set, and one use of `Subtarget-&gt;enableSubRegLiveness()`
has been changed to `MRI-&gt;subRegLivenessEnabled()` to make sure the
option properly applies.</pre>
</div>
</content>
</entry>
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