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<title>llvm-project.git/llvm/lib/Target/PowerPC/PPCRegisterInfo.cpp, branch main</title>
<subtitle>Unnamed repository; edit this file 'description' to name the repository.
</subtitle>
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<entry>
<title>CodeGen: Remove TRI argument from getRegClass (#158225)</title>
<updated>2025-11-10T23:43:55+00:00</updated>
<author>
<name>Matt Arsenault</name>
<email>Matthew.Arsenault@amd.com</email>
</author>
<published>2025-11-10T23:43:55+00:00</published>
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<id>55422e804b3bd2fcb1a330673af40240e359540f</id>
<content type='text'>
TargetInstrInfo now directly holds a reference to TargetRegisterInfo
and does not need TRI passed in anywhere.</content>
<content type='xhtml'>
<div xmlns='http://www.w3.org/1999/xhtml'>
<pre>
TargetInstrInfo now directly holds a reference to TargetRegisterInfo
and does not need TRI passed in anywhere.</pre>
</div>
</content>
</entry>
<entry>
<title>CodeGen: Remove MachineFunction argument from getRegClass (#158188)</title>
<updated>2025-09-12T10:22:02+00:00</updated>
<author>
<name>Matt Arsenault</name>
<email>Matthew.Arsenault@amd.com</email>
</author>
<published>2025-09-12T10:22:02+00:00</published>
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<id>7289f2cd0c371b2539faa628ec0eea58fa61892c</id>
<content type='text'>
This is a low level utility to parse the MCInstrInfo and should
not depend on the state of the function.</content>
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<pre>
This is a low level utility to parse the MCInstrInfo and should
not depend on the state of the function.</pre>
</div>
</content>
</entry>
<entry>
<title>CodeGen: Remove MachineFunction argument from getPointerRegClass (#158185)</title>
<updated>2025-09-12T09:18:50+00:00</updated>
<author>
<name>Matt Arsenault</name>
<email>Matthew.Arsenault@amd.com</email>
</author>
<published>2025-09-12T09:18:50+00:00</published>
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<id>2331fbb01978463a218d80883d29a003fdef6e14</id>
<content type='text'>
getPointerRegClass is a layering violation. Its primary purpose
is to determine how to interpret an MCInstrDesc's operands RegClass
fields. This should be context free, and only depend on the subtarget.
The model of this is also wrong, since this should be an
instruction / operand specific property, not a global pointer class.
Remove the the function argument to help stage removal of this hook
and avoid introducing any new obstacles to replacing it.

The remaining uses of the function were to get the subtarget, which
TargetRegisterInfo already belongs to. A few targets needed new
subtarget derived properties copied there.</content>
<content type='xhtml'>
<div xmlns='http://www.w3.org/1999/xhtml'>
<pre>
getPointerRegClass is a layering violation. Its primary purpose
is to determine how to interpret an MCInstrDesc's operands RegClass
fields. This should be context free, and only depend on the subtarget.
The model of this is also wrong, since this should be an
instruction / operand specific property, not a global pointer class.
Remove the the function argument to help stage removal of this hook
and avoid introducing any new obstacles to replacing it.

The remaining uses of the function were to get the subtarget, which
TargetRegisterInfo already belongs to. A few targets needed new
subtarget derived properties copied there.</pre>
</div>
</content>
</entry>
<entry>
<title>[PowerPC] fix lowering of SPILL_CRBIT on pwr9 and pwr10 (#146424)</title>
<updated>2025-08-08T07:24:22+00:00</updated>
<author>
<name>Paul Murphy</name>
<email>murp@redhat.com</email>
</author>
<published>2025-08-08T07:24:22+00:00</published>
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<id>5f864560a6514bb74ecc1e0c7d3ff8c412228bfe</id>
<content type='text'>
If a copy exists between creation of a crbit and a spill, machine-cp
may delete the copy since it seems unaware of the relation between a cr
and crbit. A fix was previously made for the generic ppc64 lowering. It
should be applied to the pwr9 and pwr10 variants too.

Likewise, relax and extend the pwr8 test to verify pwr9 and pwr10
codegen too.

This fixes #143989.</content>
<content type='xhtml'>
<div xmlns='http://www.w3.org/1999/xhtml'>
<pre>
If a copy exists between creation of a crbit and a spill, machine-cp
may delete the copy since it seems unaware of the relation between a cr
and crbit. A fix was previously made for the generic ppc64 lowering. It
should be applied to the pwr9 and pwr10 variants too.

Likewise, relax and extend the pwr8 test to verify pwr9 and pwr10
codegen too.

This fixes #143989.</pre>
</div>
</content>
</entry>
<entry>
<title>[PowerPC]  Add code to spill and restore DMRp registers (#142443)</title>
<updated>2025-06-18T17:50:57+00:00</updated>
<author>
<name>Lei Huang</name>
<email>lei@ca.ibm.com</email>
</author>
<published>2025-06-18T17:50:57+00:00</published>
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<id>82acd8c377e9ed267195afdbde16eedebabc648c</id>
<content type='text'>
</content>
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<pre>
</pre>
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</content>
</entry>
<entry>
<title>[PowerPC][NFC] Update lowering STXVP to STXV in Oct word spilling (#143953)</title>
<updated>2025-06-12T19:47:02+00:00</updated>
<author>
<name>Lei Huang</name>
<email>lei@ca.ibm.com</email>
</author>
<published>2025-06-12T19:47:02+00:00</published>
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<id>c317eda6e3785037f16a746a1096c2cca82d9455</id>
<content type='text'>
Simpliy handling for spilling of acc reg with stx by removing explicit
register arithmetic and clean up code gen for register mapping used in
stxvp spilling.

Relanding: https://github.com/llvm/llvm-project/pull/142220</content>
<content type='xhtml'>
<div xmlns='http://www.w3.org/1999/xhtml'>
<pre>
Simpliy handling for spilling of acc reg with stx by removing explicit
register arithmetic and clean up code gen for register mapping used in
stxvp spilling.

Relanding: https://github.com/llvm/llvm-project/pull/142220</pre>
</div>
</content>
</entry>
<entry>
<title>Revert "[PowerPC][NFC] Update lowering STXVP to STXV in Oct word spil… (#143948)</title>
<updated>2025-06-12T18:56:25+00:00</updated>
<author>
<name>Lei Huang</name>
<email>lei@ca.ibm.com</email>
</author>
<published>2025-06-12T18:56:25+00:00</published>
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<id>df7db441d4e97568a5cbf830b0810512bb702159</id>
<content type='text'>
…ling (#142220)"

This reverts commit edf636afe405ff90da7bf1834aa334bd52bc861e.
checked in wrong branch.</content>
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<div xmlns='http://www.w3.org/1999/xhtml'>
<pre>
…ling (#142220)"

This reverts commit edf636afe405ff90da7bf1834aa334bd52bc861e.
checked in wrong branch.</pre>
</div>
</content>
</entry>
<entry>
<title>[PowerPC][NFC] Update lowering STXVP to STXV in Oct word spilling (#142220)</title>
<updated>2025-06-12T18:38:54+00:00</updated>
<author>
<name>Lei Huang</name>
<email>lei@ca.ibm.com</email>
</author>
<published>2025-06-12T18:38:54+00:00</published>
<link rel='alternate' type='text/html' href='https://git.belthelziquor.com/llvm-project.git/commit/?id=edf636afe405ff90da7bf1834aa334bd52bc861e'/>
<id>edf636afe405ff90da7bf1834aa334bd52bc861e</id>
<content type='text'>
Remove explicit register arithmetic from spilling ACC and STXVP code.</content>
<content type='xhtml'>
<div xmlns='http://www.w3.org/1999/xhtml'>
<pre>
Remove explicit register arithmetic from spilling ACC and STXVP code.</pre>
</div>
</content>
</entry>
<entry>
<title>[PowerPC] Spill and restore DMR register (#141530)</title>
<updated>2025-06-02T17:11:39+00:00</updated>
<author>
<name>Lei Huang</name>
<email>lei@ca.ibm.com</email>
</author>
<published>2025-06-02T17:11:39+00:00</published>
<link rel='alternate' type='text/html' href='https://git.belthelziquor.com/llvm-project.git/commit/?id=05f1ca7d17e46510a41992cedc6ff062940aa7b4'/>
<id>05f1ca7d17e46510a41992cedc6ff062940aa7b4</id>
<content type='text'>
Add spilling and restoring of DMR registers.</content>
<content type='xhtml'>
<div xmlns='http://www.w3.org/1999/xhtml'>
<pre>
Add spilling and restoring of DMR registers.</pre>
</div>
</content>
</entry>
<entry>
<title>[PowerPC][NFC] clean up if-else block in PPCRegisterInfo.cpp (#140084)</title>
<updated>2025-05-22T17:37:05+00:00</updated>
<author>
<name>Lei Huang</name>
<email>lei@ca.ibm.com</email>
</author>
<published>2025-05-22T17:37:05+00:00</published>
<link rel='alternate' type='text/html' href='https://git.belthelziquor.com/llvm-project.git/commit/?id=a40762cd78d5d254d2298d74ead839732f4c8b7f'/>
<id>a40762cd78d5d254d2298d74ead839732f4c8b7f</id>
<content type='text'>
Move all if-else conditions into a switch stmt for handling spills.</content>
<content type='xhtml'>
<div xmlns='http://www.w3.org/1999/xhtml'>
<pre>
Move all if-else conditions into a switch stmt for handling spills.</pre>
</div>
</content>
</entry>
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