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<title>llvm-project.git/llvm/lib/Target/PowerPC/PPCMachineFunctionInfo.h, branch users/nico/python-2</title>
<subtitle>Unnamed repository; edit this file 'description' to name the repository.
</subtitle>
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<entry>
<title>[PowerPC] Tune AIX shared library TLS model at function level (#84132)</title>
<updated>2024-05-09T01:50:36+00:00</updated>
<author>
<name>Felix (Ting Wang)</name>
<email>Ting.Wang.SH@ibm.com</email>
</author>
<published>2024-05-09T01:50:36+00:00</published>
<link rel='alternate' type='text/html' href='https://git.belthelziquor.com/llvm-project.git/commit/?id=ea126aebdc9d8205016f355d85dbf1c15f2f4b28'/>
<id>ea126aebdc9d8205016f355d85dbf1c15f2f4b28</id>
<content type='text'>
Under some circumstance (library loaded with the main program), TLS
initial-exec model can be applied to local-dynamic access(es). We
could use some simple heuristic to decide the update at function level:
* If there is equal or less than a number of TLS local-dynamic access(es)
in the function, use TLS initial-exec model. (the threshold which default to
1 is controlled by hidden option)</content>
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<pre>
Under some circumstance (library loaded with the main program), TLS
initial-exec model can be applied to local-dynamic access(es). We
could use some simple heuristic to decide the update at function level:
* If there is equal or less than a number of TLS local-dynamic access(es)
in the function, use TLS initial-exec model. (the threshold which default to
1 is controlled by hidden option)</pre>
</div>
</content>
</entry>
<entry>
<title>CodeGen: Don't lazily construct MachineFunctionInfo</title>
<updated>2022-12-21T15:49:32+00:00</updated>
<author>
<name>Matt Arsenault</name>
<email>Matthew.Arsenault@amd.com</email>
</author>
<published>2020-06-18T13:00:16+00:00</published>
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<id>69e75ae695d9ef1360a2a1fbefd6e0e0456c3f7b</id>
<content type='text'>
This fixes what I consider to be an API flaw I've tripped over
multiple times. The point this is constructed isn't well defined, so
depending on where this is first called, you can conclude different
information based on the MachineFunction. For example, the AMDGPU
implementation inspected the MachineFrameInfo on construction for the
stack objects and if the frame has calls. This kind of worked in
SelectionDAG which visited all allocas up front, but broke in
GlobalISel which hasn't visited any of the IR when arguments are
lowered.

I've run into similar problems before with the MIR parser and trying
to make use of other MachineFunction fields, so I think it's best to
just categorically disallow dependency on the MachineFunction state in
the constructor and to always construct this at the same time as the
MachineFunction itself.

A missing feature I still could use is a way to access an custom
analysis pass on the IR here.
</content>
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<pre>
This fixes what I consider to be an API flaw I've tripped over
multiple times. The point this is constructed isn't well defined, so
depending on where this is first called, you can conclude different
information based on the MachineFunction. For example, the AMDGPU
implementation inspected the MachineFrameInfo on construction for the
stack objects and if the frame has calls. This kind of worked in
SelectionDAG which visited all allocas up front, but broke in
GlobalISel which hasn't visited any of the IR when arguments are
lowered.

I've run into similar problems before with the MIR parser and trying
to make use of other MachineFunction fields, so I think it's best to
just categorically disallow dependency on the MachineFunction state in
the constructor and to always construct this at the same time as the
MachineFunction itself.

A missing feature I still could use is a way to access an custom
analysis pass on the IR here.
</pre>
</div>
</content>
</entry>
<entry>
<title>llvm-reduce: Add cloning of target MachineFunctionInfo</title>
<updated>2022-06-07T14:14:48+00:00</updated>
<author>
<name>Matt Arsenault</name>
<email>Matthew.Arsenault@amd.com</email>
</author>
<published>2022-04-16T02:35:53+00:00</published>
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<id>cc5a1b3dd9039d50f6b9caa679d60398f0cec65f</id>
<content type='text'>
MIR support is totally unusable for AMDGPU without this, since the set
of reserved registers is set from fields here.

Add a clone method to MachineFunctionInfo. This is a subtle variant of
the copy constructor that is required if there are any MIR constructs
that use pointers. Specifically, at minimum fields that reference
MachineBasicBlocks or the MachineFunction need to be adjusted to the
values in the new function.
</content>
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<pre>
MIR support is totally unusable for AMDGPU without this, since the set
of reserved registers is set from fields here.

Add a clone method to MachineFunctionInfo. This is a subtle variant of
the copy constructor that is required if there are any MIR constructs
that use pointers. Specifically, at minimum fields that reference
MachineBasicBlocks or the MachineFunction need to be adjusted to the
values in the new function.
</pre>
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</content>
</entry>
<entry>
<title>[AIX][XCOFF] emit vector info of traceback table.</title>
<updated>2021-06-14T15:15:22+00:00</updated>
<author>
<name>zhijian</name>
<email>zhijian@ca.ibm.com</email>
</author>
<published>2021-06-14T15:15:22+00:00</published>
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<id>7ed515d16803f12fc06258ebf8a405931dc8a637</id>
<content type='text'>
Summary:

emit vector info of traceback table.

Reviewers: Jason Liu,Hubert Tong
Differential Revision: https://reviews.llvm.org/D93659
</content>
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<pre>
Summary:

emit vector info of traceback table.

Reviewers: Jason Liu,Hubert Tong
Differential Revision: https://reviews.llvm.org/D93659
</pre>
</div>
</content>
</entry>
<entry>
<title>[PowerPC] Add ROP Protection to prologue and epilogue</title>
<updated>2021-05-13T17:54:44+00:00</updated>
<author>
<name>Stefan Pintilie</name>
<email>stefanp@ca.ibm.com</email>
</author>
<published>2021-05-13T14:58:59+00:00</published>
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<id>54310fc176fde539b15f3cc95d4a3555df446ff6</id>
<content type='text'>
Added hashst to the prologue and hashchk to the epilogue.
The hash for the prologue and epilogue must always be stored as the first
element in the local variable space on the stack.

Reviewed By: nemanjai, #powerpc

Differential Revision: https://reviews.llvm.org/D99377
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<pre>
Added hashst to the prologue and hashchk to the epilogue.
The hash for the prologue and epilogue must always be stored as the first
element in the local variable space on the stack.

Reviewed By: nemanjai, #powerpc

Differential Revision: https://reviews.llvm.org/D99377
</pre>
</div>
</content>
</entry>
<entry>
<title>[AIX][XCOFF] emit traceback table for function in aix</title>
<updated>2020-12-11T22:50:25+00:00</updated>
<author>
<name>diggerlin</name>
<email>digger.llvm@gmail.com</email>
</author>
<published>2020-12-11T22:50:25+00:00</published>
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<id>997d286f2d0fde66f6eb825932eb06ca3b83607f</id>
<content type='text'>
SUMMARY:
 1. added a new option -xcoff-traceback-table to control whether generate traceback table for function.
 2. implement the functionality of emit traceback table of a function.

Reviewers: hubert.reinterpretcast, Jason Liu
Differential Revision: https://reviews.llvm.org/D92398
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<pre>
SUMMARY:
 1. added a new option -xcoff-traceback-table to control whether generate traceback table for function.
 2. implement the functionality of emit traceback table of a function.

Reviewers: hubert.reinterpretcast, Jason Liu
Differential Revision: https://reviews.llvm.org/D92398
</pre>
</div>
</content>
</entry>
<entry>
<title>[PowerPC] Remove support for VRSAVE save/restore/update.</title>
<updated>2020-09-30T14:05:53+00:00</updated>
<author>
<name>Sean Fertile</name>
<email>sd.fertile@gmail.com</email>
</author>
<published>2020-09-30T13:56:55+00:00</published>
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<id>dfb717da1f794c235b81a985a57dc238c82318e6</id>
<content type='text'>
After removal of Darwin as a PowerPC subtarget, the VRSAVE
save/restore/spill/update code is no longer needed by any supported
subtarget, so remove it while keeping support for vrsave and related instruction
aliases for inline asm. I've pre-commited tests to document the existing vrsave
handling in relation to @llvm.eh.unwind.init and inline asm usage, as
well as a test which shows a beahviour change on AIX related to
returning vector type as we were wrongly emiting VRSAVE_UPDATE on AIX.
</content>
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<div xmlns='http://www.w3.org/1999/xhtml'>
<pre>
After removal of Darwin as a PowerPC subtarget, the VRSAVE
save/restore/spill/update code is no longer needed by any supported
subtarget, so remove it while keeping support for vrsave and related instruction
aliases for inline asm. I've pre-commited tests to document the existing vrsave
handling in relation to @llvm.eh.unwind.init and inline asm usage, as
well as a test which shows a beahviour change on AIX related to
returning vector type as we were wrongly emiting VRSAVE_UPDATE on AIX.
</pre>
</div>
</content>
</entry>
<entry>
<title>PPC: Don't store function in PPCFunctionInfo</title>
<updated>2020-06-30T20:08:51+00:00</updated>
<author>
<name>Matt Arsenault</name>
<email>Matthew.Arsenault@amd.com</email>
</author>
<published>2020-06-30T19:36:19+00:00</published>
<link rel='alternate' type='text/html' href='https://git.belthelziquor.com/llvm-project.git/commit/?id=d9f0c3663f023ce2935b18dda3c3c7cbd7bf666b'/>
<id>d9f0c3663f023ce2935b18dda3c3c7cbd7bf666b</id>
<content type='text'>
Continue migrating targets from depending on the MachineFunction
during the initial construction.
</content>
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<div xmlns='http://www.w3.org/1999/xhtml'>
<pre>
Continue migrating targets from depending on the MachineFunction
during the initial construction.
</pre>
</div>
</content>
</entry>
<entry>
<title>CodeGen: Use Register</title>
<updated>2020-05-19T21:56:55+00:00</updated>
<author>
<name>Matt Arsenault</name>
<email>Matthew.Arsenault@amd.com</email>
</author>
<published>2020-05-19T17:01:19+00:00</published>
<link rel='alternate' type='text/html' href='https://git.belthelziquor.com/llvm-project.git/commit/?id=4dad4914f7d5232639e64ffbc816078184f1462c'/>
<id>4dad4914f7d5232639e64ffbc816078184f1462c</id>
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</content>
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<pre>
</pre>
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</content>
</entry>
<entry>
<title>[PowerPC] Remove support for SplitCSR.</title>
<updated>2020-05-14T14:32:17+00:00</updated>
<author>
<name>Sean Fertile</name>
<email>sd.fertile@gmail.com</email>
</author>
<published>2020-05-14T14:31:01+00:00</published>
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<id>ce4ebc14a8963e58f08a6ab6c5ce4096469d570d</id>
<content type='text'>
SplitCSR was only suppored for functions with CXX_FAST_TLS calling
convention. Clang only emits that calling convention for Darwin which is
no longer supported by the PowerPC backend. Another IR producer could
use the calling convention, but considering the calling convention is
meant to be an optimization and the codegen for SplitCSR can be
attrocious on Power (see the modifed lit test) it is best to remove it
and codegen CXX_FAST_TLS same as the C calling convention.

Differential Revision: https://reviews.llvm.org/D79018
</content>
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<pre>
SplitCSR was only suppored for functions with CXX_FAST_TLS calling
convention. Clang only emits that calling convention for Darwin which is
no longer supported by the PowerPC backend. Another IR producer could
use the calling convention, but considering the calling convention is
meant to be an optimization and the codegen for SplitCSR can be
attrocious on Power (see the modifed lit test) it is best to remove it
and codegen CXX_FAST_TLS same as the C calling convention.

Differential Revision: https://reviews.llvm.org/D79018
</pre>
</div>
</content>
</entry>
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