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<title>llvm-project.git/llvm/lib/Target/PowerPC/PPCInstrInfo.cpp, branch users/wangpc-pp/spr/main.aarch64-remove-usage-of-postrascheduler</title>
<subtitle>Unnamed repository; edit this file 'description' to name the repository.
</subtitle>
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<entry>
<title>[PowerPC][AIX] 64-bit large code-model support for toc-data (#90619)</title>
<updated>2024-05-21T18:00:24+00:00</updated>
<author>
<name>Zaara Syeda</name>
<email>syzaara@ca.ibm.com</email>
</author>
<published>2024-05-21T18:00:24+00:00</published>
<link rel='alternate' type='text/html' href='https://git.belthelziquor.com/llvm-project.git/commit/?id=194e7cc7aabe2ffb153ca66527ffb6b500fa4c50'/>
<id>194e7cc7aabe2ffb153ca66527ffb6b500fa4c50</id>
<content type='text'>
This patch adds support for toc-data for 64-bit large code-model on AIX.
The sequence ADDIStocHA8/ADDItocL8 is used to access the data directly
from the TOC.
When emitting the instruction ADDIStocHA8, we check if the symbol has
toc-data attribute before creating a toc entry for it. When emitting the
instruction ADDItocL8, we use the LA8 instruction to load the address.</content>
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<pre>
This patch adds support for toc-data for 64-bit large code-model on AIX.
The sequence ADDIStocHA8/ADDItocL8 is used to access the data directly
from the TOC.
When emitting the instruction ADDIStocHA8, we check if the symbol has
toc-data attribute before creating a toc entry for it. When emitting the
instruction ADDItocL8, we use the LA8 instruction to load the address.</pre>
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</content>
</entry>
<entry>
<title>[CodeGen] Make the parameter TRI required in some functions. (#85968)</title>
<updated>2024-04-24T13:24:14+00:00</updated>
<author>
<name>Xu Zhang</name>
<email>simonzgx@gmail.com</email>
</author>
<published>2024-04-24T13:24:14+00:00</published>
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<id>f6d431f208c0fa48827eac40e7acf788346a9967</id>
<content type='text'>
Fixes #82659

There are some functions, such as `findRegisterDefOperandIdx` and  `findRegisterDefOperand`, that have too many default parameters. As a result, we have encountered some issues due to the lack of TRI  parameters, as shown in issue #82411.

Following @RKSimon 's suggestion, this patch refactors 9 functions, including `{reads, kills, defines, modifies}Register`,  `registerDefIsDead`, and `findRegister{UseOperandIdx, UseOperand, DefOperandIdx, DefOperand}`, adjusting the order of the TRI parameter and making it required. In addition, all the places that call these functions have also been updated correctly to ensure no additional impact.

After this, the caller of these functions should explicitly know whether to pass the `TargetRegisterInfo` or just a `nullptr`.</content>
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<pre>
Fixes #82659

There are some functions, such as `findRegisterDefOperandIdx` and  `findRegisterDefOperand`, that have too many default parameters. As a result, we have encountered some issues due to the lack of TRI  parameters, as shown in issue #82411.

Following @RKSimon 's suggestion, this patch refactors 9 functions, including `{reads, kills, defines, modifies}Register`,  `registerDefIsDead`, and `findRegister{UseOperandIdx, UseOperand, DefOperandIdx, DefOperand}`, adjusting the order of the TRI parameter and making it required. In addition, all the places that call these functions have also been updated correctly to ensure no additional impact.

After this, the caller of these functions should explicitly know whether to pass the `TargetRegisterInfo` or just a `nullptr`.</pre>
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</content>
</entry>
<entry>
<title>[PowerPC] 32-bit large code-model support for toc-data (#85129)</title>
<updated>2024-04-17T13:24:53+00:00</updated>
<author>
<name>Zaara Syeda</name>
<email>syzaara@ca.ibm.com</email>
</author>
<published>2024-04-17T13:24:53+00:00</published>
<link rel='alternate' type='text/html' href='https://git.belthelziquor.com/llvm-project.git/commit/?id=76ad2897480a85532eee93daf041246881772693'/>
<id>76ad2897480a85532eee93daf041246881772693</id>
<content type='text'>
This patch adds the pseudo op ADDItocL for 32-bit large code-model
support for toc-data.</content>
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<pre>
This patch adds the pseudo op ADDItocL for 32-bit large code-model
support for toc-data.</pre>
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</content>
</entry>
<entry>
<title>[MachineCombiner][NFC] Split target-dependent patterns</title>
<updated>2024-04-11T04:20:27+00:00</updated>
<author>
<name>Pengcheng Wang</name>
<email>wangpengcheng.pp@bytedance.com</email>
</author>
<published>2024-04-11T04:20:27+00:00</published>
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<id>b5640369337e98e573c949080ed4a4061ec6ec9a</id>
<content type='text'>
We split target-dependent MachineCombiner patterns into their target
folder.

This makes MachineCombiner much more target-independent.

Reviewers:
davemgreen, asavonic, rotateright, RKSimon, lukel97, LuoYuanke, topperc, mshockwave, asi-sc

Reviewed By: topperc, mshockwave

Pull Request: https://github.com/llvm/llvm-project/pull/87991
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<pre>
We split target-dependent MachineCombiner patterns into their target
folder.

This makes MachineCombiner much more target-independent.

Reviewers:
davemgreen, asavonic, rotateright, RKSimon, lukel97, LuoYuanke, topperc, mshockwave, asi-sc

Reviewed By: topperc, mshockwave

Pull Request: https://github.com/llvm/llvm-project/pull/87991
</pre>
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</content>
</entry>
<entry>
<title>[PowerPC][NFC] Rename ADDItocL to match the 64-bit naming convention (#85099)</title>
<updated>2024-03-13T15:57:07+00:00</updated>
<author>
<name>Zaara Syeda</name>
<email>syzaara@ca.ibm.com</email>
</author>
<published>2024-03-13T15:57:07+00:00</published>
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<id>cc761a7c356178009d186e70740ccb53bf0c6deb</id>
<content type='text'>
In preparation of adding a similar instruction for large code model on
AIX for 32-bit, rename the exisitng ADDItocL 64-instruction to ADDItocL8
to match the naming convention of other instructions with 32-bit and
64-bit variants.</content>
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<pre>
In preparation of adding a similar instruction for large code model on
AIX for 32-bit, rename the exisitng ADDItocL 64-instruction to ADDItocL8
to match the naming convention of other instructions with 32-bit and
64-bit variants.</pre>
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</content>
</entry>
<entry>
<title>[Codegen] Make Width in getMemOperandsWithOffsetWidth a LocationSize. (#83875)</title>
<updated>2024-03-06T17:40:13+00:00</updated>
<author>
<name>David Green</name>
<email>david.green@arm.com</email>
</author>
<published>2024-03-06T17:40:13+00:00</published>
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<id>44be5a7fdc20a7f90d63dc18699a470e900bd3ba</id>
<content type='text'>
This is another part of #70452 which makes getMemOperandsWithOffsetWidth
use a LocationSize for Width, as opposed to the unsigned it currently
uses. The advantages on it's own are not super high if
getMemOperandsWithOffsetWidth usually uses known sizes, but if the
values can come from an MMO it can help be more accurate in case they
are Unknown (and in the future, scalable).</content>
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<pre>
This is another part of #70452 which makes getMemOperandsWithOffsetWidth
use a LocationSize for Width, as opposed to the unsigned it currently
uses. The advantages on it's own are not super high if
getMemOperandsWithOffsetWidth usually uses known sizes, but if the
values can come from an MMO it can help be more accurate in case they
are Unknown (and in the future, scalable).</pre>
</div>
</content>
</entry>
<entry>
<title>[PowerPC] Support local-dynamic TLS relocation on AIX (#66316)</title>
<updated>2024-03-01T00:09:40+00:00</updated>
<author>
<name>Felix (Ting Wang)</name>
<email>Ting.Wang.SH@ibm.com</email>
</author>
<published>2024-03-01T00:09:40+00:00</published>
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<id>5b058709536dd883980722ee000bb7b8c7b2cd8b</id>
<content type='text'>
Supports TLS local-dynamic on AIX, generates below sequence of code:

```
.tc foo[TC],foo[TL]@ld # Variable offset, ld relocation specifier
.tc mh[TC],mh[TC]@ml # Module handle for the caller
lwz 3,mh[TC]\(2\) $$ For 64-bit: ld 3,mh[TC]\(2\)
bla .__tls_get_mod # Modifies r0,r3,r4,r5,r11,lr,cr0
#r3 = &amp;TLS for module
lwz 4,foo[TC]\(2\) $$ For 64-bit: ld 4,foo[TC]\(2\)
add 5,3,4 # Compute &amp;foo
.rename mh[TC], "\_$TLSML" # Symbol for the module handle must have the name "_$TLSML"
```

---------

Co-authored-by: tingwang &lt;tingwang@tingwangs-MBP.lan&gt;
Co-authored-by: tingwang &lt;tingwang@tingwangs-MacBook-Pro.local&gt;</content>
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<pre>
Supports TLS local-dynamic on AIX, generates below sequence of code:

```
.tc foo[TC],foo[TL]@ld # Variable offset, ld relocation specifier
.tc mh[TC],mh[TC]@ml # Module handle for the caller
lwz 3,mh[TC]\(2\) $$ For 64-bit: ld 3,mh[TC]\(2\)
bla .__tls_get_mod # Modifies r0,r3,r4,r5,r11,lr,cr0
#r3 = &amp;TLS for module
lwz 4,foo[TC]\(2\) $$ For 64-bit: ld 4,foo[TC]\(2\)
add 5,3,4 # Compute &amp;foo
.rename mh[TC], "\_$TLSML" # Symbol for the module handle must have the name "_$TLSML"
```

---------

Co-authored-by: tingwang &lt;tingwang@tingwangs-MBP.lan&gt;
Co-authored-by: tingwang &lt;tingwang@tingwangs-MacBook-Pro.local&gt;</pre>
</div>
</content>
</entry>
<entry>
<title>[TTI] Use Register in isLoadFromStackSlot and isStoreToStackSlot [nfc] (#80339)</title>
<updated>2024-02-02T01:52:35+00:00</updated>
<author>
<name>Philip Reames</name>
<email>preames@rivosinc.com</email>
</author>
<published>2024-02-02T01:52:35+00:00</published>
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<id>3ff7caea330def5f8433e3eb2b89ae3fe5e9f9a0</id>
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<pre>
</pre>
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</entry>
<entry>
<title>[PowerPC][X86] Make cpu id builtins target independent and lower for PPC (#68919)</title>
<updated>2024-01-26T16:24:50+00:00</updated>
<author>
<name>Nemanja Ivanovic</name>
<email>nemanja.i.ibm@gmail.com</email>
</author>
<published>2024-01-26T16:24:50+00:00</published>
<link rel='alternate' type='text/html' href='https://git.belthelziquor.com/llvm-project.git/commit/?id=67c1c1dbb6cd473ce302079d0b3791ff461b7bba'/>
<id>67c1c1dbb6cd473ce302079d0b3791ff461b7bba</id>
<content type='text'>
Make __builtin_cpu_{init|supports|is} target independent and provide an
opt-in query for targets that want to support it. Each target is still
responsible for their specific lowering/code-gen. Also provide code-gen
for PowerPC.

I originally proposed this in https://reviews.llvm.org/D152914 and this
addresses the comments I received there.

---------

Co-authored-by: Nemanja Ivanovic &lt;nemanjaivanovic@nemanjas-air.kpn&gt;
Co-authored-by: Nemanja Ivanovic &lt;nemanja@synopsys.com&gt;</content>
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<pre>
Make __builtin_cpu_{init|supports|is} target independent and provide an
opt-in query for targets that want to support it. Each target is still
responsible for their specific lowering/code-gen. Also provide code-gen
for PowerPC.

I originally proposed this in https://reviews.llvm.org/D152914 and this
addresses the comments I received there.

---------

Co-authored-by: Nemanja Ivanovic &lt;nemanjaivanovic@nemanjas-air.kpn&gt;
Co-authored-by: Nemanja Ivanovic &lt;nemanja@synopsys.com&gt;</pre>
</div>
</content>
</entry>
<entry>
<title>[NFC] Rename TargetInstrInfo::FoldImmediate to TargetInstrInfo::foldImmediate and simplify implementation for X86</title>
<updated>2024-01-26T12:50:58+00:00</updated>
<author>
<name>Shengchen Kan</name>
<email>shengchen.kan@intel.com</email>
</author>
<published>2024-01-26T12:29:35+00:00</published>
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<pre>
</pre>
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