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<title>llvm-project.git/llvm/lib/Target/PowerPC/PPCInstrInfo.cpp, branch main</title>
<subtitle>Unnamed repository; edit this file 'description' to name the repository.
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<entry>
<title>CodeGen: Remove TRI arguments from stack load/store hooks (#158240)</title>
<updated>2025-11-11T00:24:39+00:00</updated>
<author>
<name>Matt Arsenault</name>
<email>Matthew.Arsenault@amd.com</email>
</author>
<published>2025-11-11T00:24:39+00:00</published>
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<id>1f3f522866ae483836cd39c13695a0ab41b547d5</id>
<content type='text'>
This is directly available in TargetInstrInfo</content>
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<pre>
This is directly available in TargetInstrInfo</pre>
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</entry>
<entry>
<title>CodeGen: Keep reference to TargetRegisterInfo in TargetInstrInfo (#158224)</title>
<updated>2025-11-10T22:40:39+00:00</updated>
<author>
<name>Matt Arsenault</name>
<email>Matthew.Arsenault@amd.com</email>
</author>
<published>2025-11-10T22:40:39+00:00</published>
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<id>11ab23c33db5c990489023c91260435db288efd8</id>
<content type='text'>
Both conceptually belong to the same subtarget, so it should not
be necessary to pass in the context TargetRegisterInfo to any
TargetInstrInfo member. Add this reference so those superfluous
arguments can be removed.

Most targets placed their TargetRegisterInfo as a member
in TargetInstrInfo. A few had this owned by the TargetSubtargetInfo,
so unify all targets to look the same.</content>
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<pre>
Both conceptually belong to the same subtarget, so it should not
be necessary to pass in the context TargetRegisterInfo to any
TargetInstrInfo member. Add this reference so those superfluous
arguments can be removed.

Most targets placed their TargetRegisterInfo as a member
in TargetInstrInfo. A few had this owned by the TargetSubtargetInfo,
so unify all targets to look the same.</pre>
</div>
</content>
</entry>
<entry>
<title>[CodeGen] Rename isReallyTriviallyReMaterializable [nfc]</title>
<updated>2025-09-23T18:58:37+00:00</updated>
<author>
<name>Philip Reames</name>
<email>preames@rivosinc.com</email>
</author>
<published>2025-09-23T15:07:37+00:00</published>
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<id>8b7a76a2ace31bbd27909c1ff99b18f888d40408</id>
<content type='text'>
.. to isReMaterializableImpl.  The "Really" naming has always been
awkward, and we're working towards removing the "Trivial" part now,
so go ehead and remove both pieces in a single rename.

Note that this doesn't change any aspect of the current
implementation; we still "mostly" only return instructions which
are trivial (meaning no virtual register uses), but some targets
do lie about that today.
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<pre>
.. to isReMaterializableImpl.  The "Really" naming has always been
awkward, and we're working towards removing the "Trivial" part now,
so go ehead and remove both pieces in a single rename.

Note that this doesn't change any aspect of the current
implementation; we still "mostly" only return instructions which
are trivial (meaning no virtual register uses), but some targets
do lie about that today.
</pre>
</div>
</content>
</entry>
<entry>
<title>PPC: Replace PointerLikeRegClass with RegClassByHwMode (#158777)</title>
<updated>2025-09-19T14:46:54+00:00</updated>
<author>
<name>Matt Arsenault</name>
<email>Matthew.Arsenault@amd.com</email>
</author>
<published>2025-09-19T14:46:54+00:00</published>
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</content>
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<pre>
</pre>
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</content>
</entry>
<entry>
<title>CodeGen: Pass SubtargetInfo to TargetGenInstrInfo constructors (#157337)</title>
<updated>2025-09-08T03:12:19+00:00</updated>
<author>
<name>Matt Arsenault</name>
<email>Matthew.Arsenault@amd.com</email>
</author>
<published>2025-09-08T03:12:19+00:00</published>
<link rel='alternate' type='text/html' href='https://git.belthelziquor.com/llvm-project.git/commit/?id=727e9f5ea5b2bb9d2fa37619ad2f19b21af7ce4d'/>
<id>727e9f5ea5b2bb9d2fa37619ad2f19b21af7ce4d</id>
<content type='text'>
This will make it possible for tablegen to make subtarget
dependent decisions without adding new arguments to every
target.

---------

Co-authored-by: Sergei Barannikov &lt;barannikov88@gmail.com&gt;</content>
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<pre>
This will make it possible for tablegen to make subtarget
dependent decisions without adding new arguments to every
target.

---------

Co-authored-by: Sergei Barannikov &lt;barannikov88@gmail.com&gt;</pre>
</div>
</content>
</entry>
<entry>
<title>PPC: Fix missing const on TargetInstrInfo's subtarget reference (#157201)</title>
<updated>2025-09-06T00:13:49+00:00</updated>
<author>
<name>Matt Arsenault</name>
<email>Matthew.Arsenault@amd.com</email>
</author>
<published>2025-09-06T00:13:49+00:00</published>
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<id>ccbcee14c8651fc0f69834f3211a6c20cac0ed2f</id>
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</content>
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<pre>
</pre>
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</entry>
<entry>
<title>[PowerPC] Add DMR and WACC COPY support (#149129)</title>
<updated>2025-08-27T15:07:24+00:00</updated>
<author>
<name>Maryam Moghadas</name>
<email>maryammo@ca.ibm.com</email>
</author>
<published>2025-08-27T15:07:24+00:00</published>
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<id>242d51afe59ec87c31c35eb07c34075866269bd8</id>
<content type='text'>
This patch updates PPCInstrInfo::copyPhysReg to support DMR and WACC
register classes and extends the PPCVSXCopy pass to handle specific WACC
copy patterns.</content>
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<pre>
This patch updates PPCInstrInfo::copyPhysReg to support DMR and WACC
register classes and extends the PPCVSXCopy pass to handle specific WACC
copy patterns.</pre>
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</content>
</entry>
<entry>
<title>[PowerPC]  Add code to spill and restore DMRp registers (#142443)</title>
<updated>2025-06-18T17:50:57+00:00</updated>
<author>
<name>Lei Huang</name>
<email>lei@ca.ibm.com</email>
</author>
<published>2025-06-18T17:50:57+00:00</published>
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<id>82acd8c377e9ed267195afdbde16eedebabc648c</id>
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</content>
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<pre>
</pre>
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</content>
</entry>
<entry>
<title>[PowerPC] Spill and restore DMR register (#141530)</title>
<updated>2025-06-02T17:11:39+00:00</updated>
<author>
<name>Lei Huang</name>
<email>lei@ca.ibm.com</email>
</author>
<published>2025-06-02T17:11:39+00:00</published>
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<id>05f1ca7d17e46510a41992cedc6ff062940aa7b4</id>
<content type='text'>
Add spilling and restoring of DMR registers.</content>
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<pre>
Add spilling and restoring of DMR registers.</pre>
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</content>
</entry>
<entry>
<title>[PowerPC] Update DMF VSX ACC data transfer instructions (#138897)</title>
<updated>2025-05-26T16:47:12+00:00</updated>
<author>
<name>Lei Huang</name>
<email>lei@ca.ibm.com</email>
</author>
<published>2025-05-26T16:47:12+00:00</published>
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<id>4b09eedf7b95c4e0b073a82ca6a60c033c17f27b</id>
<content type='text'>
For cpu=future, acc registers no longer overlap VSRs and are prefixed
with `dm`. The original, xxmfacc/xxmtacc instructions are now extended
menemonics to it's dm* equivalents.</content>
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<pre>
For cpu=future, acc registers no longer overlap VSRs and are prefixed
with `dm`. The original, xxmfacc/xxmtacc instructions are now extended
menemonics to it's dm* equivalents.</pre>
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</content>
</entry>
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