llvm-project.git/llvm/lib/Target/PowerPC/PPCInstrFormats.td, branch users/nico/python-2

Reland "[PowerPC] Add error for incorrect use of memory operands (#114277)" (#115958)

2024-11-14T03:24:19+00:00

Commit 93589057830b2c3c35500ee8cac25c717a1e98f9 was reverted because it
caused a failure with test `lld :: ELF/ppc64-local-exec-tls.s`. This
relands the commit with a fix for the test.

Revert "[PowerPC] Add error for incorrect use of memory operands (#114277)"

2024-11-12T09:03:06+00:00

This commit broke a test on a couple bots
lld :: ELF/ppc64-local-exec-tls.s

This reverts commit 93589057830b2c3c35500ee8cac25c717a1e98f9.

[PowerPC] Add error for incorrect use of memory operands (#114277)

2024-11-12T08:00:06+00:00

If an instruction doesn't support memory operands, but one is provided,
an error should be raised. And conversely, if an instruction requires a
memory operand, but none is given, an error should be raised.

[PowerPC] Add a set of extended mnemonics that are missing from Power 10. (#73003)

2023-12-07T18:40:00+00:00

This patch adds the majority of the missing extended mnemonics that were
introduced in Power 10.

The only extended mnemonics that were not added are related to the plq
and pstq instructions. These will be added in a separate patch as the
instructions themselves would also have to be added.

[PowerPC] Add the SCV instruction. (#68063)

2023-10-05T16:51:04+00:00

The SCV instruciton was added on PowerPC on Power 9. This patch adds the
SCV so that it may be used as part of inline asm but does not provide
patterns for it or scheduling information.

Co-authored-by: Stefan Pintilie

[PowerPC][MC] Recognize tlbilx and its mnemonics

2023-08-02T03:10:46+00:00

This fixes issue 64080. tlbilx exists in ISA 2.07 Book III-E. Since
contents of Book III-E were eliminated after ISA 3.0, tlbilx does not
exist in ISA 3.0 and ISA 3.1.

Reviewed By: nickdesaulniers

Differential Revision: https://reviews.llvm.org/D156204

[PowerPC] Add DFP test instruction definitions and MC tests

2023-07-14T18:00:37+00:00

Adding the td definitions, and their associated assembly and disassembly
test cases for the decimal floating point test instructions defined in
section 5.6.3 of ISA 3.1

Reviewed By: lei, amyk

Differential Revision: https://reviews.llvm.org/D154606

[PowerPC] Add DFP format instructions definitions and MC tests

2023-07-14T16:09:24+00:00

Add td definitions and asm/disasm tests for the dfp format
instructions in ISA 3.1 section 5.6.6

Reviewed By: stefanp, kamaub

Differential Revision: https://reviews.llvm.org/D154465

[PowerPC] Add DFP quantum adjustment instruction definitions and MC tests

2023-07-04T19:10:37+00:00

Add td definitions and asm/disasm tests for the quantum adjustment
instructions in ISA 3.1 section 5.6.4

Reviewed By: stefanp

Differential Revision: https://reviews.llvm.org/D154369

[PowerPC] Switch to by-name matching for instructions (part 2 of 2).

2023-02-02T20:28:45+00:00

This is a follow-on to https://reviews.llvm.org/D134073.

Currently, all of the "memri"-style complex operands, which contain
both a register and an immediate, are encoded into a single field in
the instruction definition. This requires complex encoders/decoders,
and instruction definitions that insert and extract the correct parts
of the bits.

Now, switch to naming and encoding/decoding the sub-operands
separately.

Thus, we can now disable useDeprecatedPositionallyEncodedOperands.

Reviewed By: barannikov88

Differential Revision: https://reviews.llvm.org/D137670