Support the following packed BCD builtins for PowerPC. ``` __builtin_national2packed - Conversion of National format to Packed decimal format. __builtin_packed2national - Conversion of Packed decimal format to national format. __builtin_packed2zoned - Conversion of Packed decimal format to Zoned decimal format. __builtin_zoned2packed - Conversion of Zoned decimal format to Packed decimal format. ``` ### Prototypes: `vector unsigned char __builtin_national2packed(vector unsigned char a, unsigned char b);` `vector unsigned char __builtin_packed2zoned(vector unsigned char, unsigned char);` `vector unsigned char __builtin_zoned2packed(vector unsigned char, unsigned char);` The condition for the 2nd parameter is consistent over all the 3 prototypes (0 or 1 only). `vector unsigned char __builtin_packed2national(vector unsigned char);` Co-authored-by: himadhith <himadhith.v@ibm.com> Co-authored-by: Tony Varghese <tonypalampalliyil@gmail.com>
Improve codegen for vectors modulo additions. Reviewed By: nemanjai Differential Revision: https://reviews.llvm.org/D154447
This is a follow-on to https://reviews.llvm.org/D134073. After https://reviews.llvm.org/D137653 we can now switch the PPC target away from positional operand matching. This patch fixes all of the "easy" cases. While this changes a large number of lines of tablegen source, it results in only a single non-comment change in the code generated by tablegen: the (unused) codegen-only "MTVRSAVEv" instruction was previously incorrectly encoding operand 0, and now encodes (correctly) operand 1. Changes which result in generated-code changes have been split off into the next (smaller) patch, for ease of review. Reviewed By: barannikov88 Differential Revision: https://reviews.llvm.org/D137661
vperm instruction requires the data to be in the Altivec registers, if one of the vector operands is not used after this vperm instruction then it can be substituted by xxperm which doubles the number of available registers. Reviewed By: stefanp Differential Revision: https://reviews.llvm.org/D133700
This patch fixes the following two bugs in `PPCInstrInfo::isSignOrZeroExtended` helper, which is used from sign-/zero-extension elimination in PPCMIPeephole pass. - Registers defined by load with update (e.g. LBZU) were identified as already sign or zero-extended. But it is true only for the first def (loaded value) and not for the second def (i.e. updated pointer). - Registers defined by ORIS/XORIS were identified as already sign-extended. But, it is not true for sign extension depending on the immediate (while it is ok for zero extension). To handle the first case, the parameter for the helpers is changed from `MachineInstr` to a register number to distinguish first and second defs. Also, this patch moves the initialization of PPCMIPeepholePass to allow mir test case. Reviewed By: nemanjai Differential Revision: https://reviews.llvm.org/D40554
Support for builtins that use bcdadd./bcdsub. to add/subtract Binary Coded Decimal values as well as to determine validity and compare BCD values. Differential revision: https://reviews.llvm.org/D114088
The instruction has similar semantics to vbpermq but for doublewords. It was added in Power9 and the ABI documents the builtin. Differential revision: https://reviews.llvm.org/D107899
These patterns are missing even though the underlying instruction doesn't really care about the type. Added these patterns to resolve https://bugs.llvm.org/show_bug.cgi?id=50084
This instruction is a nop on all server cores (certainly on all cores that AIX supports) so it is fine to emit a nop instead of it. In fact, that is exactly what XL emits. So we emit a nop on AIX and we leave the codegen as is on other platforms since there may indeed be cores out there for which this actually does some prefetching.
This patch introduces a new infrastructure that is used to select the load and store instructions in the PPC backend. The primary motivation is that the current implementation of selecting load/stores is dependent on the ordering of patterns in TableGen. Given this limitation, we are not able to easily and reliably generate the P10 prefixed load and stores instructions (such as when the immediates that fit within 34-bits). This refactoring is meant to provide us with more control over the patterns/different forms to exploit, as well as eliminating dependency of pattern declaration in TableGen. The idea of this refactoring is that it introduces a set of addressing modes that correspond to different instruction formats of a particular load and store instruction, along with a set of common flags that describes a load/store. Whenever a load/store instruction is being selected, we analyze the instruction and compute a set of flags for it. The computed flags are then used to select the most optimal load/store addressing mode. This patch is the first of a series of patches to be committed - it contains the initial implementation of the refactored load/store selection infrastructure and also updates P8/P9 patterns to adopt this infrastructure. The idea is that incremental patches will add more implementation and support, and eventually the old implementation will be removed. Differential Revision: https://reviews.llvm.org/D93370