llvm-project.git/llvm/lib/Target/PowerPC/PPCFrameLowering.h, branch users/nico/python-2

[llvm] Consistently respect `naked` fn attribute in `TargetFrameLowering::hasFP()` (#106014)

2024-10-18T05:35:42+00:00

Some targets (e.g. PPC and Hexagon) already did this. I think it's best
to do this consistently so that frontend authors don't run into
inconsistent results when they emit `naked` functions. For example, in
Zig, we had to change our emit code to also set `frame-pointer=none` to
get reliable results across targets.

Note: I don't have commit access.

[PowerPC] Spill non-volatile registers required for traceback table (#71115)

2024-05-07T20:23:37+00:00

On AIX we need to spill all [rfv]N-[rfv]31 when a function clobbers
[rfv]N so that the traceback table contains accurate information.

[PEI][PowerPC] Fix false alarm of stack size limit (#65559)

2023-09-08T07:16:00+00:00

PPC64 allows stack size up to ((2^63)-1) bytes. Currently llc reports
```
warning: stack frame size (4294967568) exceeds limit (4294967295) in function 'main'
```
if the stack allocated is larger than 4G.

[PowerPC] Use int64_t to represent stack object offset and frame size

2021-08-23T02:13:21+00:00

This is the first step to enable PPC64 support huge frame size(>2G). Also fix an assertion error for frame size, i.e.,`int x; !isInt<32>(x);` should be always evaluated false, so the guard code for frame size is impossible to hit.

Reviewed By: jsji

Differential Revision: https://reviews.llvm.org/D107435

[PowerPC] Use mtvsrdd to put callee-saved GPR into VSR

2021-04-20T08:43:24+00:00

This patch exploits mtvsrdd instruction (available in ISA3.0+) to save
two callee-saved GPR registers into a single VSR, making it more
efficient.

Reviewed By: jsji, nemanjai

Differential Revision: https://reviews.llvm.org/D62565

[PowerPC] Implement probing for prologue

2020-07-04T03:07:08+00:00

This patch is part of supporting `-fstack-clash-protection`. Implemented
probing when emitting prologue.

Differential Revision: https://reviews.llvm.org/D81460

CodeGen: Use Register

2020-05-19T21:56:55+00:00

ArrayRef'ize restoreCalleeSavedRegisters. NFCI.

2020-02-29T08:50:23+00:00

restoreCalleeSavedRegisters can mutate the contents of the
CalleeSavedInfos, so use a MutableArrayRef.

[PowerPC][AIX] Spill/restore the callee-saved condition register bits.

2020-02-24T16:24:46+00:00

Extends the existing support for spilling and restoring the condition
register to the linkage area for 32-bit targets, and enables for AIX.

Differential Revision: https://reviews.llvm.org/D74349

ArrayRef'ize spillCalleeSavedRegisters. NFCI.

2020-02-08T11:19:23+00:00