1. The PR proceeds with a backend target hook to allow front-ends to determine what target features are available in a compilation based on the CPU name. 2. Fix a backend target feature bug that supports HTM for Power8/9/10/11. However, HTM is only supported on Power8/9 according to the ISA. 3. All target features that are hardcoded in PPC.cpp can be retrieved from the backend target feature. I have double-checked that the hardcoded logic for inferring target features from the CPU in the frontend(PPC.cpp) is the same as in PPC.td. The reland patch addressed the comment https://github.com/llvm/llvm-project/pull/137670#discussion_r2143541120
This reverts commit 9208b343e962b9f1140ee345c0050a3920bdcbf2. TargetParser shouldn't re-run the PPC subtarget tablegen target, it should define its own `-gen-ppc-target-def` rule like all the other targets do in llvm/include/llvm/TargetParser/CMakeLists.txt . One user reported that there are incorrect CMake dependencies after this change, so I will roll this back in the meantime.
1. The PR proceeds with a backend target hook to allow front-ends to determine what target features are available in a compilation based on the CPU name. 2. Fix a backend target feature bug that supports HTM for Power8/9/10/11. However, HTM is only supported on Power8/9 according to the ISA. 3. All target features that are hardcoded in PPC.cpp can be retrieved from the backend target feature. I have double-checked that the hardcoded logic for inferring target features from the CPU in the frontend(PPC.cpp) is the same as in PPC.td.
For cpu=future, we want to auto generate stxvp instructions by default.
The new TableGen warning introduced in https://github.com/llvm/llvm-project/commit/951292be2c21bc903e63729338d872a878d2d49c shows the following warnings: ``` warning: Processor future contains duplicate feature 'predictable-select-expensive' warning: Processor pwr10 contains duplicate feature 'predictable-select-expensive' warning: Processor pwr11 contains duplicate feature 'predictable-select-expensive' warning: Processor pwr9 contains duplicate feature 'predictable-select-expensive' ```
Fixes: https://github.com/llvm/llvm-project/issues/71030 Bug only happens in 64bit involving spills. Since we don't know when the spill will happen, all instructions in the chain used to deduce sign extension for eliminating 'extsw' will need to be promoted to 64-bit pseudo instructions. The following instruction will promoted in PPCMIPeepholes: EXTSH, LHA, ISEL to EXTSH8, LHA8, ISEL8
Use PPC `MatchRegisterName()` that is auto generated by table gen.
This PR adds support for -mcpu=pwr11/power11 and -mtune=pwr11/power11 in clang and llvm.
The Prefix instruction is introduced on PowerPC ISA3_1. In the PR, 1. The `FeaturePrefixInstrs` do not imply the `FeatureP8Vector` ,`FeatureP9Vector` . 2. `FeaturePrefixInstrs` implies only the FeatureISA3_1. 3. For the prefix instructions `paddi` and `pli` , they have `Predicates = [PrefixInstrs] ` 4. For the prefix instructions `plfs` and `plfd`, they have `Predicates = [PrefixInstrs, HasFPU] ` 5. For the prefix instructions "plxv` , "plxssp` and `plxsd` , they have `Predicates = [PrefixInstrs, HasP10Vector]` Fixes #62372
Under some circumstance (library loaded with the main program), TLS initial-exec model can be applied to local-dynamic access(es). We could use some simple heuristic to decide the update at function level: * If there is equal or less than a number of TLS local-dynamic access(es) in the function, use TLS initial-exec model. (the threshold which default to 1 is controlled by hidden option)