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<title>llvm-project.git/llvm/lib/Target/Mips/MipsSubtarget.cpp, branch users/nico/python-2</title>
<subtitle>Unnamed repository; edit this file 'description' to name the repository.
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<entry>
<title>Mips/X86: Use reportFatalUsageError for subtarget construction errors (#142028)</title>
<updated>2025-05-30T06:03:50+00:00</updated>
<author>
<name>Matt Arsenault</name>
<email>Matthew.Arsenault@amd.com</email>
</author>
<published>2025-05-30T06:03:50+00:00</published>
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<entry>
<title>[SelectionDAG] Add empty implementation of SelectionDAGInfo to some targets (#119968)</title>
<updated>2024-12-16T12:13:46+00:00</updated>
<author>
<name>Sergei Barannikov</name>
<email>barannikov88@gmail.com</email>
</author>
<published>2024-12-16T12:13:46+00:00</published>
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#119969 adds a couple of new methods to this class, which will need to
be overridden by these targets.

Part of #119709.

Pull Request: https://github.com/llvm/llvm-project/pull/119968
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#119969 adds a couple of new methods to this class, which will need to
be overridden by these targets.

Part of #119709.

Pull Request: https://github.com/llvm/llvm-project/pull/119968
</pre>
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</entry>
<entry>
<title>[Mips] Remove unused includes (NFC) (#116499)</title>
<updated>2024-11-16T20:13:26+00:00</updated>
<author>
<name>Kazu Hirata</name>
<email>kazu@google.com</email>
</author>
<published>2024-11-16T20:13:26+00:00</published>
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Identified with misc-include-cleaner.</content>
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<pre>
Identified with misc-include-cleaner.</pre>
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</entry>
<entry>
<title>[ARM][Mips][PowerPC] Remove unnecessary static_cast creating GISel InstructionSelector. NFC</title>
<updated>2024-07-10T17:28:32+00:00</updated>
<author>
<name>Craig Topper</name>
<email>craig.topper@sifive.com</email>
</author>
<published>2024-07-10T17:23:11+00:00</published>
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<content type='text'>
Some targets only pass a TargetMachine &amp; to their subtarget constructor
and require a static_cast to their target-specific TargetMachine subclass
to create *InstructionSelector.

These 3 targets already have the correct TargetMachine subclass
reference so no cast is needed.
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Some targets only pass a TargetMachine &amp; to their subtarget constructor
and require a static_cast to their target-specific TargetMachine subclass
to create *InstructionSelector.

These 3 targets already have the correct TargetMachine subclass
reference so no cast is needed.
</pre>
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</entry>
<entry>
<title>MIPS: Support -m(no-)unaligned-access for r6 (#85174)</title>
<updated>2024-03-20T06:18:24+00:00</updated>
<author>
<name>YunQiang Su</name>
<email>syq@debian.org</email>
</author>
<published>2024-03-20T06:18:24+00:00</published>
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<content type='text'>
MIPSr6 ISA requires normal load/store instructions support
misunaligned memory access, while it is not always do so
by hardware. On some microarchitectures or some corner cases
it may need support by OS.

Don't confuse with pre-R6's lwl/lwr famlily: MIPSr6 doesn't
support them, instead, r6 requires lw instruction support
misunaligned memory access. So, if -mstrict-align is used for
pre-R6, lwl/lwr won't be disabled.

If -mstrict-align is used for r6 and the access is not well
aligned, some lb/lh instructions will be used to replace lw.
This is useful for OS kernels.

To be back-compatible with GCC, -m(no-)unaligned-access are also
added as Neg-Alias of -m(no-)strict-align.</content>
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<pre>
MIPSr6 ISA requires normal load/store instructions support
misunaligned memory access, while it is not always do so
by hardware. On some microarchitectures or some corner cases
it may need support by OS.

Don't confuse with pre-R6's lwl/lwr famlily: MIPSr6 doesn't
support them, instead, r6 requires lw instruction support
misunaligned memory access. So, if -mstrict-align is used for
pre-R6, lwl/lwr won't be disabled.

If -mstrict-align is used for r6 and the access is not well
aligned, some lb/lh instructions will be used to replace lw.
This is useful for OS kernels.

To be back-compatible with GCC, -m(no-)unaligned-access are also
added as Neg-Alias of -m(no-)strict-align.</pre>
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</content>
</entry>
<entry>
<title>[NFC][CodeGen] Change CodeGenOpt::Level/CodeGenFileType into enum classes (#66295)</title>
<updated>2023-09-14T21:10:14+00:00</updated>
<author>
<name>Arthur Eubanks</name>
<email>aeubanks@google.com</email>
</author>
<published>2023-09-14T21:10:14+00:00</published>
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This will make it easy for callers to see issues with and fix up calls
to createTargetMachine after a future change to the params of
TargetMachine.

This matches other nearby enums.

For downstream users, this should be a fairly straightforward
replacement,
e.g. s/CodeGenOpt::Aggressive/CodeGenOptLevel::Aggressive
or s/CGFT_/CodeGenFileType::</content>
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This will make it easy for callers to see issues with and fix up calls
to createTargetMachine after a future change to the params of
TargetMachine.

This matches other nearby enums.

For downstream users, this should be a fairly straightforward
replacement,
e.g. s/CodeGenOpt::Aggressive/CodeGenOptLevel::Aggressive
or s/CGFT_/CodeGenFileType::</pre>
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</entry>
<entry>
<title>MIPS: allow o32 abi with 64bit CPU and 64 abi with 32bit triple</title>
<updated>2023-05-16T22:31:37+00:00</updated>
<author>
<name>YunQiang Su</name>
<email>wzssyqa@gmail.com</email>
</author>
<published>2023-05-16T22:31:37+00:00</published>
<link rel='alternate' type='text/html' href='https://git.belthelziquor.com/llvm-project.git/commit/?id=7983f8aca82e258174849f1cc6a70029353e9887'/>
<id>7983f8aca82e258174849f1cc6a70029353e9887</id>
<content type='text'>
In general, MIPS support ELF format like
   ELF 32-bit LSB relocatable, MIPS, MIPS64 rel2 version 1 (SYSV)
and Linux's VDSO uses it.

Currently clang stop CMDs like
    clang -march=mips64r2 -mabi=32

While it is not needed now, since the the backend support the combination now.

This patch also allows something like
     clang --target=mipsel-linux-gnu -mabi=64
Since the triple can convert to right 64bit one automaticly.

Reviewed By: MaskRay

Differential Revision: https://reviews.llvm.org/D146269
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<pre>
In general, MIPS support ELF format like
   ELF 32-bit LSB relocatable, MIPS, MIPS64 rel2 version 1 (SYSV)
and Linux's VDSO uses it.

Currently clang stop CMDs like
    clang -march=mips64r2 -mabi=32

While it is not needed now, since the the backend support the combination now.

This patch also allows something like
     clang --target=mipsel-linux-gnu -mabi=64
Since the triple can convert to right 64bit one automaticly.

Reviewed By: MaskRay

Differential Revision: https://reviews.llvm.org/D146269
</pre>
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</entry>
<entry>
<title>[Support] Make report_fatal_error respect its GenCrashDiag argument so it doesn't generate a backtrace</title>
<updated>2022-05-30T18:19:23+00:00</updated>
<author>
<name>Nuno Lopes</name>
<email>nuno.lopes@tecnico.ulisboa.pt</email>
</author>
<published>2022-05-30T18:16:06+00:00</published>
<link rel='alternate' type='text/html' href='https://git.belthelziquor.com/llvm-project.git/commit/?id=80b3dcc045f8ea6e5e532d8891bbf1305bce89e8'/>
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<content type='text'>
There are a few places where we use report_fatal_error when the input is broken.
Currently, this function always crashes LLVM with an abort signal, which
then triggers the backtrace printing code.
I think this is excessive, as wrong input shouldn't give a link to
LLVM's github issue URL and tell users to file a bug report.
We shouldn't print a stack trace either.

This patch changes report_fatal_error so it uses exit() rather than
abort() when its argument GenCrashDiag=false.

Reviewed by: nikic, MaskRay, RKSimon

Differential Revision: https://reviews.llvm.org/D126550
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There are a few places where we use report_fatal_error when the input is broken.
Currently, this function always crashes LLVM with an abort signal, which
then triggers the backtrace printing code.
I think this is excessive, as wrong input shouldn't give a link to
LLVM's github issue URL and tell users to file a bug report.
We shouldn't print a stack trace either.

This patch changes report_fatal_error so it uses exit() rather than
abort() when its argument GenCrashDiag=false.

Reviewed by: nikic, MaskRay, RKSimon

Differential Revision: https://reviews.llvm.org/D126550
</pre>
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</content>
</entry>
<entry>
<title>[MIPS] Initial support for MIPS-I load delay slots</title>
<updated>2022-04-07T00:02:29+00:00</updated>
<author>
<name>Simon Dardis</name>
<email>simon.dardis@gmail.com</email>
</author>
<published>2022-04-06T23:31:33+00:00</published>
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<id>303c180199b73eb9c2840d05c92afeb9326e2e15</id>
<content type='text'>
LLVM so far has only supported the MIPS-II and above architectures. MIPS-II is pretty close to MIPS-I, the major difference
being that "load" instructions always take one extra instruction slot to propogate to registers. This patch adds support for
MIPS-I by adding hazard handling for load delay slots, alongside MIPSR6 forbidden slots and FPU slots, inserting a NOP
instruction between a load and any instruction immediately following that reads the load's destination register. I also
included a simple regression test. Since no existing tests target MIPS-I, those all still pass.

Issue ref: https://github.com/simias/psx-sdk-rs/issues/1

I also tested by building a simple demo app with Clang and running it in an emulator.

Patch by: @impiaaa

Differential Revision: https://reviews.llvm.org/D122427
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<pre>
LLVM so far has only supported the MIPS-II and above architectures. MIPS-II is pretty close to MIPS-I, the major difference
being that "load" instructions always take one extra instruction slot to propogate to registers. This patch adds support for
MIPS-I by adding hazard handling for load delay slots, alongside MIPSR6 forbidden slots and FPU slots, inserting a NOP
instruction between a load and any instruction immediately following that reads the load's destination register. I also
included a simple regression test. Since no existing tests target MIPS-I, those all still pass.

Issue ref: https://github.com/simias/psx-sdk-rs/issues/1

I also tested by building a simple demo app with Clang and running it in an emulator.

Patch by: @impiaaa

Differential Revision: https://reviews.llvm.org/D122427
</pre>
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</content>
</entry>
<entry>
<title>Move TargetRegistry.(h|cpp) from Support to MC</title>
<updated>2021-10-08T21:51:48+00:00</updated>
<author>
<name>Reid Kleckner</name>
<email>rnk@google.com</email>
</author>
<published>2021-10-08T17:48:15+00:00</published>
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<content type='text'>
This moves the registry higher in the LLVM library dependency stack.
Every client of the target registry needs to link against MC anyway to
actually use the target, so we might as well move this out of Support.

This allows us to ensure that Support doesn't have includes from MC/*.

Differential Revision: https://reviews.llvm.org/D111454
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<pre>
This moves the registry higher in the LLVM library dependency stack.
Every client of the target registry needs to link against MC anyway to
actually use the target, so we might as well move this out of Support.

This allows us to ensure that Support doesn't have includes from MC/*.

Differential Revision: https://reviews.llvm.org/D111454
</pre>
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